HD64F2145 datasheet(27/829 Pages) RENESAS

27 / 829 page

Rev. 2.0, 08/02, page xxv of xxxviii

Section 10 14-Bit PWM Timer (PWMX)

Figure 10.1 PWM (D/A) Block Diagram....................................................................................227

Figure 10.2 PWM D/A Operation ...............................................................................................2 34

Figure 10.3 Output Waveform (OS = 0, DADR corresponds to T

L) ...........................................236

Figure 10.4 Output Waveform (OS = 1, DADR corresponds to T

H) ...........................................237

Figure 10.5 D/A Data Register Configuration when CFS = 1 ....................................................237

Figure 10.6 Output Waveform when DADR = H’0207 (OS = 1) ...............................................238

Section 11 16-Bit Free-Running Timer (FRT)

Figure 11.1 Block Diagram of 16-Bit Free-Running Timer........................................................242

Figure 11.2 Example of Pulse Output .........................................................................................253

Figure 11.3 Increment Timing with Internal Clock Source ........................................................253

Figure 11.4 Increment Timing with External Clock Source .......................................................254

Figure 11.5 Timing of Output Compare A Output......................................................................254

Figure 11.6 Clearing of FRC by Compare-Match A Signal........................................................255

Figure 11.7 Input Capture Input Signal Timing (Usual Case) ....................................................255

Figure 11.8 Input Capture Input Signal Timing (When ICRA to ICRD are Read) .....................256

Figure 11.9 Buffered Input Capture Timing ...............................................................................256

Figure 11.10 Buffered Input Capture Timing (BUFEA = 1).......................................................257

Figure 11.11 Timing of Input Capture Flag (ICFA, ICFB, ICFC, or ICFD) Setting ..................257

Figure 11.12 Timing of Output Compare Flag (OCFA or OCFB) Setting .................................258

Figure 11.13 Timing of Overflow Flag (OVF) Setting ...............................................................258

Figure 11.14 OCRA Automatic Addition Timing.......................................................................259

Figure 11.15 Timing of Input Capture Mask Signal Setting .......................................................259

Figure 11.16 Timing of Input Capture Mask Signal Clearing.....................................................260

Figure 11.17 FRC Write-Clear Conflict......................................................................................261

Figure 11.18 FRC Write-Increment Conflict ..............................................................................262

Figure 11.19 Conflict between OCR Write and Compare-Match

(When Automatic Addition Function is Not Used)...............................................263

Figure 11.20 Conflict between OCRAR/OCRAF Write and Compare-Match

(When Automatic Addition Function is Used)......................................................264

Section 12 8-Bit Timer (TMR)

Figure 12.1 Block Diagram of 8-Bit Timers (TMR_0 and TMR_1)...........................................268

Figure 12.2 Block Diagram of 8-Bit Timers (TMR_Y and TMR_X).........................................269

Figure 12.3 Pulse Output Example .............................................................................................282

Figure 12.4 Count Timing for Internal Clock Input ....................................................................283

Figure 12.5 Count Timing for External Clock Input (Both Edges).............................................283

Figure 12.6 Timing of CMF Setting at Compare-Match.............................................................284

Figure 12.7 Timing of Toggled Timer Output by Compare-Match A Signal .............................284

Figure 12.8 Timing of Counter Clear by Compare-Match..........................................................285

Figure 12.9 Timing of Counter Clear by External Reset Input ...................................................285

Figure 12.10 Timing of OVF Flag Setting ..................................................................................286

Figure 12.11 Timing of Input Capture Operation .......................................................................288

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