HD64F2145 datasheet(17/829 Pages) RENESAS

17 / 829 page

Rev. 2.0, 08/02, page xv of xxxviii

13.2

Input/Output Pins ..............................................................................................................299

13.3

Register Descriptions.........................................................................................................299

13.3.1 Timer Connection Register I (TCONRI)..............................................................300

13.3.2 Timer Connection Register O (TCONRO)...........................................................303

13.3.3 Timer Connection Register S (TCONRS) ............................................................305

13.3.4 Edge Sense Register (SEDGR) ............................................................................307

13.4

Operation ...........................................................................................................................309

13.4.1 PWM Decoding (PDC Signal Generation)...........................................................309

13.4.2 Clamp Waveform Generation (CL1/CL2/CL3 Signal Generation)......................310

13.4.3 Measurement of 8-Bit Timer Divided Waveform Period.....................................312

13.4.4 2fH Modification of IHI Signal............................................................................314

13.4.5 IVI Signal Fall Modification and IHI Synchronization ........................................316

13.4.6 Internal Synchronization Signal Generation

(IHG/IVG/CL4 Signal Generation) ......................................................................317

13.4.7 HSYNCO Output .................................................................................................320

13.4.8 VSYNCO Output .................................................................................................321

13.4.9 CBLANK Output .................................................................................................322

13.5

Usage Note ........................................................................................................................323

13.5.1 Module Stop Mode Setting...................................................................................323

Section 14 Watchdog Timer (WDT) .................................................................325

14.1

Features .............................................................................................................................325

14.2

Input/Output Pins ..............................................................................................................327

14.3

Register Descriptions.........................................................................................................327

14.3.1 Timer Counter (TCNT) ........................................................................................327

14.3.2 Timer Control/Status Register (TCSR) ................................................................328

14.4

Operation ...........................................................................................................................332

14.4.1 Watchdog Timer Mode ........................................................................................332

14.4.2 Interval Timer Mode ............................................................................................334

14.4.3

5(62 Signal Output Timing................................................................................335

14.5

Interrupt Sources ...............................................................................................................335

14.6

Usage Notes.......................................................................................................................336

14.6.1 Notes on Register Access .....................................................................................336

14.6.2 Conflict between Timer Counter (TCNT) Write and Increment ..........................337

14.6.3 Changing Values of CKS2 to CKS0 Bits .............................................................337

14.6.4 Switching between Watchdog Timer Mode and Interval Timer Mode ................337

14.6.5 System Reset by

5(62 Signal.............................................................................338

14.6.6 Counter Values during Transitions between High-Speed, Sub-Active,

and Watch Modes .................................................................................................338

Section 15 Serial Communication Interface (SCI and IrDA)............................339

15.1

Features .............................................................................................................................339

15.2

Input/Output Pins ..............................................................................................................341

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