HD64F2145 datasheet(20/829 Pages) RENESAS

20 / 829 page

Rev. 2.0, 08/02, page xviii of xxxviii

17.4.8 KCLK Fall Interrupt Operation............................................................................480

17.5

Usage Notes.......................................................................................................................481

17.5.1 KBIOE Setting and KCLK Falling Edge Detection .............................................481

17.5.2 Module Stop Mode Setting ..................................................................................481

Section 18 Host Interface X-Bus Interface (XBS) ............................................ 483

18.1

Features .............................................................................................................................483

18.2

Input/Output Pins ..............................................................................................................485

18.3

Register Descriptions ........................................................................................................486

18.3.1 System Control Register 2 (SYSCR2) .................................................................486

18.3.2 Host Interface Control Register (HICR) Host Interface Control Register 2

(HICR2)................................................................................................................488

18.3.3 Input Data Register (IDR) ....................................................................................491

18.3.4 Output Data Register 1 (ODR).............................................................................491

18.3.5 Status Register (STR)...........................................................................................492

18.4

Operation...........................................................................................................................493

18.4.1 Host Interface Activation .....................................................................................493

18.4.2 Control States .......................................................................................................495

18.4.3 A20 Gate ..............................................................................................................495

18.4.4 Host Interface Pin Shutdown Function ................................................................497

18.5

Interrupt Sources ...............................................................................................................499

18.5.1 IBF1, IBF2, IBF3, and IBF4 ................................................................................499

18.5.2 HIRQ11, HIRQ1, HIRQ12, HIRQ3, and HIRQ4 ................................................499

18.6

Usage Notes.......................................................................................................................501

18.6.1 Note on Host Interface .........................................................................................501

18.6.2 Module Stop Mode Setting ..................................................................................501

Section 19 Host Interface LPC Interface (LPC)................................................ 503

19.1

Features .............................................................................................................................503

19.2

Input/Output Pins ..............................................................................................................505

19.3

Register Descriptions ........................................................................................................506

19.3.1 Host Interface Control Registers 0 and 1 (HICR0, HICR1).................................507

19.3.2 Host Interface Control Registers 2 and 3 (HICR2, HICR3).................................514

19.3.3 LPC Channel 3 Address Register (LADR3) ........................................................517

19.3.4 Input Data Registers 1 to 3 (IDR1 to IDR3).........................................................518

19.3.5 Output Data Registers 1 to 3 (ODR1 to ODR3)...................................................519

19.3.6 Bidirectional Data Registers 0 to 15 (TWR0 to TWR15) ....................................529

19.3.7 Status Registers 1 to 3 (STR1 to STR3)...............................................................520

19.3.8 SERIRQ Control Registers 0 and 1 (SIRQCR0, SIRQCR1)................................527

19.3.9 Host Interface Select Register (HISEL) ...............................................................535

19.4

Operation...........................................................................................................................536

19.4.1 Host Interface Activation .....................................................................................536

19.4.2 LPC I/O Cycles ....................................................................................................537

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