HD64F2145 datasheet(16/829 Pages) RENESAS

16 / 829 page

Rev. 2.0, 08/02, page xiv of xxxviii

11.7.2 Conflict between FRC Write and Increment ........................................................262

11.7.3 Conflict between OCR Write and Compare-Match .............................................262

11.7.4 Switching of Internal Clock and FRC Operation .................................................264

11.7.5 Module Stop Mode Setting ..................................................................................266

Section 12 8-Bit Timer (TMR) ......................................................................... 267

12.1

Features .............................................................................................................................267

12.2

Input/Output Pins ..............................................................................................................270

12.3

Register Descriptions ........................................................................................................270

12.3.1 Timer Counter (TCNT) ........................................................................................271

12.3.2 Time Constant Register A (TCORA) ...................................................................271

12.3.3 Time Constant Register B (TCORB) ...................................................................271

12.3.4 Timer Control Register (TCR) .............................................................................272

12.3.5 Timer Control/Status Register (TCSR) ................................................................275

12.3.6 Input Capture Register (TICR).............................................................................281

12.3.7 Time Constant Register (TCORC) .......................................................................281

12.3.8 Input Capture Registers R and F (TICRR, TICRF)..............................................281

12.3.9 Timer Input Select Register (TISR) .....................................................................282

12.4

Operation...........................................................................................................................282

12.4.1 Pulse Output .........................................................................................................282

12.5

Operation Timing ..............................................................................................................283

12.5.1 TCNT Count Timing............................................................................................283

12.5.2 Timing of CMFA and CMFB Setting at Compare-Match ...................................284

12.5.3 Timing of Timer Output at Compare-Match ........................................................284

12.5.4 Timing of Counter Clear at Compare-Match .......................................................285

12.5.5 TCNT External Reset Timing ..............................................................................285

12.5.6 Timing of Overflow Flag (OVF) Setting..............................................................286

12.6

Operation with Cascaded Connection ...............................................................................286

12.6.1 16-Bit Count Mode ..............................................................................................286

12.6.2 Compare-Match Count Mode...............................................................................287

12.7

Input Capture Operation....................................................................................................287

12.8

Interrupt Sources ...............................................................................................................290

12.9

Usage Notes.......................................................................................................................291

12.9.1 Conflict between TCNT Write and Clear.............................................................291

12.9.2 Conflict between TCNT Write and Increment .....................................................292

12.9.3 Conflict between TCOR Write and Compare-Match ...........................................293

12.9.4 Conflict between Compare-Matches A and B......................................................294

12.9.5 Switching of Internal Clocks and TCNT Operation .............................................294

12.9.6 Mode Setting with Cascaded Connection ............................................................296

12.9.7 Module Stop Mode Setting ..................................................................................296

Section 13 Timer Connection............................................................................ 297

13.1

Features .............................................................................................................................297

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