Z86C34 datasheet(62/70 Pages) ZILOG

62 / 70 page

Z86C34/C35/C36/C44/C45/C46

CMOS Z8® MCUs with ASCI UART

ZiLOG

P R E L I M I N A R Y

DS007601-Z8X0499

Z8 CONTROL REGISTERS (Continued)

Figure 45. Prescaler 0 Register

(F5H: WRITE ONLY)

Figure 46. Port 2 Mode Register

(F6H: WRITE ONLY)

Figure 47. Port 3 Mode Register

(F7H: WRITE ONLY)

0 T0 Single Pass

1 T0 Modulo N

Count Mode

Reserved (Must be 0)

Prescaler Modulo

(Range: 1-64 Decimal

01-00 HEX)

R245 PRE0

P20 - P27 I/O Definition

Defines Bit as Output

Defines Bit as Input

R246 P2M

D7 D6 D5 D4 D3 D2 D1 D0

R247 P3M

0 Port 2 Pull-Ups Open Drain

1 Port 2 Push-Pull Active

0 P31, P32 Digital Mode

1 P31, P32 Analog Mode

0 P32 = Input

P35 = Output

1 P32 = DAV0/RDY0

P35 = RDY0/DAV0

00 P33 = Input

P34 = Output

01 P33 = Input

10 P34 = DM

P34 = RDY1/DAV1

0 P31 = Input (TIN)

P36 = Output (T

OUT)

1 P31 = DAV2/RDY2

P36 = RDY2/DAV2

0 P30 = Input

Reserved (must be 0)

11 P33 = DAV0/RDY0

P37 = Output

Figure 48. Port 0 and 1 Mode Register

(F8H: WRITE ONLY)

Figure 49. Interrupt Priority Register

(F9H: WRITE ONLY)

R248 P01M

P00–P03 Mode

00 Output

01 Input

1X A11–A8

Stack Selection

0 External

1 Internal

P10 - P17 Mode

00 Byte Output

01 Byte Input

10 AD7 - AD0

11 High-Impedance AD7–AD0,

AS, DS, R/W, A11–A8,

A15–A12, If Selected

P04–P07 Mode

00 Output

01 Input

1X A15–A12

External Memory Timing

0 Normal

1 Extended

For 28 pin device, the user must set:

D2=1

D3=0

D4=0

†

Interrupt Group Priority

000 Reserved

001 C > A > B

010 A > B > C

011 A > C > B

100 B > C > A

101 C > B > A

110 B > A > C

111 Reserved

IRQ3, IRQ5 Priority (Group A)

0 IRQ5 > IRQ3

1 IRQ3 > IRQ5

IRQ0, IRQ2 Priority (Group B)

0 IRQ2 > IRQ0

1 IRQ0 > IRQ2

IRQ1, IRQ4 Priority (Group C)

0 IRQ1 > IRQ4

1 IRQ4 > IRQ1

Reserved (Must be 0)

R249 IPR

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