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Z86C34 датащи(PDF) 28 Page - Zilog, Inc.

номер детали Z86C34
подробное описание детали  CMOS Z8 MCUs WITH ASCI UART OFFER EFFICIENT, COST-EFFECTIVE DESIGN FLEXIBILITY
PDF  70 Pages
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производитель  ZILOG [Zilog, Inc.]
домашняя страница  http://www.zilog.com
Logo ZILOG - Zilog, Inc.

Z86C34 датащи(HTML) 28 Page - Zilog, Inc.

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Z86C34/C35/C36/C44/C45/C46
CMOS Z8® MCUs with ASCI UART
ZiLOG
28
P R E L I M I N A R Y
DS007601-Z8X0499
PIN FUNCTIONS (Continued)
Auto Latch.
The Auto Latch places valid CMOS levels on
all CMOS inputs (except P33–P31) that are not externally
driven. Whether this level is 0 or 1 cannot be determined.
A valid CMOS level, rather than a floating node, reduces
excessive supply current flow in the input buffer. Auto
Latches are available on Port 0, Port 1, Port 2, and P30.
There are no Auto Latches on P31, P32, and P33.
Note: Deletion of all Port Auto Latches is available as a ROM
Mask option. The Auto Latch Delete option is selected
by the customer when the ROM code is submitted.
RESET (input, active Low).
Initializes the MCU. Reset is
accomplished either through Power-On Reset, Watch-Dog
Timer reset, Stop-Mode Recovery, or external reset. During
Power-On Reset and Watch-Dog Reset, the internally-gen-
erated reset is driving the RESET pin Low for the POR time.
Any devices driving the RESET line must be open-drain to
avoid damage from a possible conflict during RESET con-
ditions. RESET depends on oscillator operation to achieve
full reset conditions, except for conditions wherein a WDT
reset is permanently enabled. Pull-up is provided internally.
Note: The RESET pin is not available on devices in the 28-pin
package.
After the POR time, RESET is a Schmitt-triggered input.
During the RESET cycle, DS is held active Low while AS
cycles at a rate of TPC/2. Program execution begins at lo-
cation 000Ch, after the RESET is released. For Power-On
Reset, the reset output time is TPOR ms.
When program execution begins, AS and DS toggles only
for external memory accesses. The Z8 does not reset
WDTMR
, SMR, P2M, PCON, and P3M registers on a Stop-
Mode Recovery operation or from a WDT reset out of STOP
mode.
Figure 16. Port 3 Configuration
P34 OUT
P31
+
REF (P33)
P34
PAD
P37 OUT
P32
+
REF (P33)
0 P34, P37 Standard Output
1 P34, P37 Comparator Output
PCON
D0
P37
PAD



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