Z86C34 datasheet(48/70 Pages) ZILOG

48 / 70 page

Z86C34/C35/C36/C44/C45/C46

CMOS Z8® MCUs with ASCI UART

ZiLOG

P R E L I M I N A R Y

DS007601-Z8X0499

ASCI TRANSMIT DATA REGISTER (TDR)

(%(A)01H: READ/WRITE)

Data written to the ASCI Transmit Data Register (TDR) is

transferred to the Transmit Shift Register (TSR) as soon as

the TSR is empty. The TSR is not not software-accessible.

The ASCI transmitter is double-buffered so data can be

written to the TDR while the TSR is shifting out the previous

byte. Data can be written into and read out of the TDR. When

the TDR is read, the data transmit operation is not affected.

ASCI RECEIVE DATA REGISTER (RDR)

(%(A)02H: READ/WRITE)

When a complete incoming data byte is assembled in the

Receive Shift Register (RSR), it is automatically transferred

to the highest available location in the Receive Data FIFO.

The Receive Data Register (RDR) is the highest location in

the Receive Data FIFO. The RDRF bit in the STAT register

is set when one or more bytes is available from the FIFO.

The FIFO status for the character in the RDR is available

in the STAT register via bits 6, 5 and 4. STAT should be

read before reading the RDR. The data in both FIFO loca-

tions is popped when the character is read from the RDR.

ASCI CONTROL REGISTER A (CNTLA)

(%(A)03H: READ/WRITE)

Table 17. TDR Register Bit Functions

Bit

76543210

Transmit Data

Reset

UUUUUUUU

Table 18. RDR Register Bit Functions

Bit

76543210

Receive Data

Reset

UUUUUUUU

Table 19. CNTLA Register Bit Functions

Bit

Multiprocessor

Enable

(MPE)

Receiver

Enable

(RE)

Transmitter

Enable

(TE)

Reserved

Multiprocessor

Bit Received

(MPBR)

MOD2 MOD1 MOD0

Error Flag

Receive

(EFR)

Mode Select

Reset

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