Z86C34 datasheet(49/70 Pages) ZILOG

49 / 70 page

Z86C34/C35/C36/C44/C45/C46

ZiLOG

CMOS Z8® MCUs with ASCI UART

DS007601-Z8X0499

P R E L I M I N A R Y

Bit 7 is the Multiprocessor Enable

The ASCI features a multiprocessor communication mode

that utilizes an extra data bit for selective communication

when a number of processors share a common serial bus.

Multiprocessor data format is selected when the MP bit in

the corresponding register is set to 1. If multiprocessor

mode is not selected (MP bit in CNTLB = 0), multiprocessor

enable (MPE) has no effect. If multiprocessor mode is se-

lected (MP bit in CNTLB = 1), MPE enables or disables the

wake-up feature as follows. If MPE is set to 1, only received

bytes in which the multiprocessor bit (MPB) = 1 are treated

as valid data characters and loaded into the receiver FIFO

with corresponding error flags in the status FIFO. Bytes

with MPB = 0 are ignored by the ASCI. If MPE is reset to

, all bytes are received by the ASCI, regardless of the state

of the MPB data bit.

Bit 6 is the Receiver Enable

When Receiver Enable(RE) is set to 1,the ASCI receiver is

enabled. When RE is reset to 0, the receiver is disabled and

any receive operation in progress is aborted. However, the

previous contents of the receiver data and status FIFO are

not affected.

Bit 5 is the Transmitter Enable

When Transmitter Enable(TE) is set to 1,the ASCI trans-

mitter is enabled. When TE is reset to 0, the transmitter is

disabled and any transmit operation in progress is aborted.

However, the previous contents of the transmitter data reg-

ister and the TDRE flag are not affected.

Bit 4 is Reserved

Bit 3 is the Multiprocessor Bit Receive

(Read only)

When multiprocessor mode is enabled (MP in CNTLB = 1),

this bit, when read, contains the value of the MPB bit for

the data byte currently available at the Receive Data Reg-

ister (the top of the receiver FIFO).

Bit 3 is the Error Flag Reset (WRITE ONLY)

When written to 0, the error flags (OVRN, FE; PE in STAT

and BRK in ASEXT) are cleared to 0. This command self-

resets, and as a result, writing EFR to a 1 is not required.

Bits 2–0 are the ASCI Data Format Mode 2,1,0

These bits program the ASCI data format.

If MOD1 = 1, parity is checked on received data and a parity

bit is appended to the data bits in the transmitted data. Parity

Even/Odd (PEO) in CNTLB selects even or odd parity.

The ASCI serial data format is illustrated in Figure 34.

Table 20. Format Mode Control Bits

Bit

Name Function

Bit = 0

Bit = 1

MOD2 Number of Data Bits

MOD1 Parity Enabled

Parity

With

Parity

MOD0 Number of Stop Bits

Figure 34. ASCI Serial Data Format

7 or 8 bits Data Field

Start

Parity

Bit

1 or 2

Stop Bit(s)

Z86C34 датащи(PDF) 49 Page - Zilog, Inc.

Z86C34 датащи(HTML) 49 Page - Zilog, Inc.

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70

датащи скачать

ссылки URL