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Z86C34 датащи(PDF) 55 Page - Zilog, Inc.

номер детали Z86C34
подробное описание детали  CMOS Z8 MCUs WITH ASCI UART OFFER EFFICIENT, COST-EFFECTIVE DESIGN FLEXIBILITY
PDF  70 Pages
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производитель  ZILOG [Zilog, Inc.]
домашняя страница  http://www.zilog.com
Logo ZILOG - Zilog, Inc.

Z86C34 датащи(HTML) 55 Page - Zilog, Inc.

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Z86C34/C35/C36/C44/C45/C46
ZiLOG
CMOS Z8® MCUs with ASCI UART
DS007601-Z8X0499
P R E L I M I N A R Y
55
Bit 2 is Reserved
When read, this bit reflects the default value 0. When
WRITE
, this bit is ignored.
Bit 1 is the Transmit Data Register Empty
TDRE = 1
indicates that the Transmit Data Register (TDR)
is empty and that the next data byte to be transmitted can
be written into the TDR. TDRE is cleared to 0 after the byte
is written to TDR, until the ASCI transfers the byte from the
TDR
to the Transmit Shift Register (TSR), and then TDRE
is again set to 1. TDRE is set to 1 at Power-On Reset.
Bit 0 is the Transmit Interrupt Enable
TIE
should be set to a 1 to enable ASCI transmit interrupt
requests. An interrupt (IRQ3) is generated when TDRE (bit
1
of the STAT register) is a 1. TIE is cleared to 0 at Power-
On Reset.
An anomaly exists that requires setting of the RIE bit to al-
low the generation of transmit interrupts. If RIE is not set,
transmit interrupts are not generated, even if TIE is set. See
Precautions.
Baud Rate Generation Summary
The application can select between one of two baud rate
generators for the ASCI. If the BRG Mode bit in the ASEXT
register is set to a 0, the SS2,1,0 bits, the DR, bit and the
PR bit in CNTLB are used to select the baud rate. If the BRG
Mode bit is set to a 1, the ASTL and ASTH registers are
used to select the baud rate.
The following formulas are used to calculate the baud rate
from the two baud rate generators:
If BRG mode = 0:
Where:
1. SCLK is the system clock.
2. PS = 1 or 0 and is bit 5 of CNTLB.
3. DIV = 1, 2, 4, 8, 16, 32 or 64 as reflected by SS2–0 in
CNTLB
.
4. DIVIDE RATIO = 16 or 64, as defined by DR in
CNTLB
.
If BRG mode = 1:
or
Where:
1. SCLK is the system clock.
2. TC is the 16-bit value programmed into ASTL and
ASTH
.
3. DIVIDE RATIO = 16 or 64, as defined by DR in
CNTLB
.
4. Baud Rate is the desired baud rate.
Baud Rate =
SCLK
(10 + 20 x PS) x DIV x Divide Ratio
Baud Rate =
SCLK
(2 x (TC + 2) x Divide Ratio
TC =
SCLK
– 2
2 x Baud Rate x Divide Ratio



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