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Z86C34 датащи(PDF) 60 Page - Zilog, Inc.

номер детали Z86C34
подробное описание детали  CMOS Z8 MCUs WITH ASCI UART OFFER EFFICIENT, COST-EFFECTIVE DESIGN FLEXIBILITY
PDF  70 Pages
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производитель  ZILOG [Zilog, Inc.]
домашняя страница  http://www.zilog.com
Logo ZILOG - Zilog, Inc.

Z86C34 датащи(HTML) 60 Page - Zilog, Inc.

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Z86C34/C35/C36/C44/C45/C46
CMOS Z8® MCUs with ASCI UART
ZiLOG
60
P R E L I M I N A R Y
DS007601-Z8X0499
EXPANDED REGISTER FILE CONTROL REGISTERS
Figure 37. Stop-Mode Recovery Register
(WRITE ONLY, except Bit D7, which is READ ONLY)
Figure 38. Stop-Mode Recovery Register2
D7
D6
D5
D4
D3
D2
D1
D0
SMR (FH) 0B
SCLK/TCLK Divide-by-16
0 OFF * *
1 ON
STOP-Mode Recovery Source
000 POR Only and/or External Reset*
001 P30
010 P31
011 P32
100 P33
101 P27
110 P2 NOR 0-3
111 P2 NOR 0-7
Stop Delay
0 OFF
1 ON*
Stop Recovery Level
0 Low*
1 High
Stop Flag (Read only)
0 POR*
1 Stop Recovery
Note: Not used in conjunction with SMR2 Source
* Default setting after RESET.
* * Default setting after RESET and STOP-Mode Recovery.
External Clock Divide by 2
0 SCLK/TCLK =XTAL/2*
1 SCLK/TCLK =XTAL
D7
D6
D5
D4
D3
D2
D1
D0
SMR2 (0F) DH
Note: Not used in conjunction with SMR Source
Stop-Mode Recovery Source 2
00 POR only*
01 AND P20,P21,P22,P23
10 AND P20,P21,P22,P23,P24,
P25,P26,P27
Reserved (Must be 0)
Figure 39. Watch-Dog Timer Mode Register
(WRITE ONLY)
D7
D6
D5
D4
D3
D2
D1
D0
WDTMR (F) 0F
WDT TAP
INT RC OSC System Clock
00
3.5 ms
128 SCLK
01
10 ms
256 SCLK
10
14 ms
512 SCLK
11
56 ms
2048 SCLK
WDT During HALT
0 OFF
1 ON
WDT During STOP
0 OFF
1 ON
XTAL1/INT RC Select for WDT
0 On-Board RC
1 XTAL
Reserved (Must be 0)
* Default setting after RESET
*
*
*
*



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