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ASX340 датащи(PDF) 75 Page - List of Unclassifed Manufacturers |
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ASX340 датащи(HTML) 75 Page - List of Unclassifed Manufacturers |
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75 / 78 page ![]() PDF: 171981479/Source: 8304342517 Aptina reserves the right to change products or specifications without notice. ASX340/MT9V139_DS Rev. C Pub. 3/11 EN 75 © 2010 Aptina Imaging Corporation All rights reserved. ASX340/MT9V139: 1/4-Inch Color CMOS NTSC/PAL Digital Image Sensor Electrical Specifications Aptina Confidential and Proprietary Preliminary Notes: 1. This table is based on I2C standard (v2.1 January 2000). Philips Semiconductor. 2. Two-wire control is I2C-compatible. 3. All values referred to VIHmin = 0.9 VDD and VILmax = 0.1VDD levels. Sensor EXCLK = 27 MHz. 4. A device must internally provide a hold time of at least 300 ns for the SDATA signal to bridge the unde- fined region of the falling edge of SCLK. 5. The maximum tHD;DAT has only to be met if the device does not stretch the LOW period (tLOW) of the SCLK signal. 6. A Fast-mode I2C-bus device can be used in a Standard-mode I2C-bus system, but the requirement tSU;DAT 250 ns must then be met. This will automatically be the case if the device does not stretch the LOW period of the SCLK signal. If such a device does stretch the LOW period of the SCLK signal, it must out- put the next data bit to the SDATA line tr max + tSU;DAT = 1000 + 250 = 1250 ns (according to the Stan- dard-mode I2C-bus specification) before the SCLK line is released. 7. Cb = total capacitance of one bus line in pF. Bus free time between a STOP and START condition tBUF 4.7 - 1.3 - μS Capacitive load for each bus line Cb - 400 - 400 pF Serial interface input pin capacitance CIN_SI - 3.3 - 3.3 pF SDATA max load capacitance CLOAD_SD - 30 - 30 pF SDATA pull-up resistor RSD 1.5 4.7 1.5 4.7 KΩ Table 51: Two-Wire Serial Bus Characteristics fEXTCLK = 27 MHz; VDD = 1.8V; VDD_IO = 2.8V; VAA = 2.8V; VAA_PIX = 2.8V; VDD_PLL = 2.8V; VDD_DAC = 2.8V; TA = 25°C Parameter Symbol Standard-Mode Fast-Mode Unit Min Max Min Max |
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