ASX340 datasheet(62/78 Pages) ETC2

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ASX340/MT9V139_DS Rev. C Pub. 3/11 EN

ASX340/MT9V139: 1/4-Inch Color CMOS NTSC/PAL Digital Image Sensor

Modes and Timing

Aptina Confidential and Proprietary

Preliminary

Figure 45:

Power Up Sequence

Notes:

1. RESET_BAR may not exceed VDD_IO + 0.3V.

2. The 2.8V plane (VAA, VAA_PIX, VDD_PLL, VDD_DAC, VDD_IO) must remain at a higher voltage than the

1.8V core voltage at all times.

Notes:

1. Xtal settling time is component-dependent (Xtal, Oscillator, and so on) and usually takes about 10mS

~100mS.

2. Hard reset time is the minimum time required after power rails are settled. Ten clock cycles are required

for the sensor itself, assuming all power rails are settled. In a circuit where Hard reset is performed by

the RC circuit, then the RC time must include the all power rail settle time and Xtal

3. This is required to load necessary patches using Flash mode (SPI) or Host mode (two-wire serial inter-

face). Loading time varies depending on the number of patches and bus speed.

Table 35:

Power Up Sequence

Definition

Symbol

Minimum

Typical

Maximum

Unit

VDD_PLL to VAA/VAA_PIX

–

μS

VAA/VAA_PIX to VDD_IO

–

μS

VDD_IO to VDD

–

μS

Xtal settle time

–

301

–mS

Hard Reset

102

–

Clock cycle

Internal Initialization

–

Patch Load (SPI or I2C)

–

4003

–mS

VDD (1.8)

VAA_PIX

VAA (2.8)

VDD_PLL

VDD_DAC (2.8)

EXTCLK

RESET_BAR

VDD_IO (2.8)

Hard Reset

Internal

(NTSC/PAL)

Initialization

Patch Config

SPI or Host

Streaming

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