ASX340 datasheet(55/78 Pages) ETC2

55 / 78 page

PDF: 171981479/Source: 8304342517

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ASX340/MT9V139_DS Rev. C Pub. 3/11 EN

ASX340/MT9V139: 1/4-Inch Color CMOS NTSC/PAL Digital Image Sensor

Modes and Timing

Aptina Confidential and Proprietary

Preliminary

Reset and Clocks

Reset

Power-up reset is asserted or de-asserted with the RESET_BAR pin, which is active LOW.

In the reset state, all control registers are set to default values. See “Device Configura-

tion” on page 31 for more details on Auto, Host, and Flash configurations.

Soft reset is asserted or de-asserted by the two-wire serial interface program. In soft-

reset mode, the two-wire serial interface and the register bus are still running. All control

registers are reset using default values.

Clocks

The ASX340/MT9V139 has two primary clocks:

• A master clock coming from the EXTCLK signal.

• In default mode, a pixel clock (PIXCLK) running at 2 * EXTCLK. In raw Bayer bypass

mode, PIXCLK runs at the same frequency as EXTCLK.

When the ASX340/MT9V139 operates in sensor stand-alone mode, the image flow pipe-

line clocks can be shut off to conserve power.

The sensor core is a master in the system. The sensor core frame rate defines the overall

image flow pipeline frame rate. Horizontal blanking and vertical blanking are influenced

by the sensor configuration, and are also a function of certain image flow pipeline func-

tions. The relationship of the primary clocks is depicted in Figure 38.

The image flow pipeline typically generates up to 16 bits per pixel—for example, YCbCr

or 565RGB—but has only an 8-bit port through which to communicate this pixel data.

To generate NTSC or PAL format images, the sensor core requires a 27 MHz clock.

Figure 38:

Primary Clock Relationships

10 bits/pixel

1 pixel/clock

16 bits/pixel

1 pixel/clock

16 bits/pixel (TYP)

0.5 pixel/clock

Colorpipe

Output Interface

Sensor

Pixel Clock

Sensor

Master Clock

EXTCLK

Sensor Core

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