ASX340 datasheet(59/78 Pages) ETC2

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PDF: 171981479/Source: 8304342517

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ASX340/MT9V139_DS Rev. C Pub. 3/11 EN

ASX340/MT9V139: 1/4-Inch Color CMOS NTSC/PAL Digital Image Sensor

Modes and Timing

Aptina Confidential and Proprietary

Preliminary

I/O Timing

Digital Output

By default, the ASX340/MT9V139 launches pixel data, FV, and LV synchronously with the

falling edge of PIXCLK. The expectation is that the user captures data, FV, and LV using

the rising edge of PIXCLK. The timing diagram is shown in Figure 42.

As an option, the polarity of the PIXCLK can be inverted from the default by program-

ming R0x0016[14].

Figure 42:

Digital Output I/O Timing

Note:

PIXCLK can be inverted from the default by programming R0x0016[14].

Table 32:

Parallel Digital Output I/O Timing

fEXTCLK = 27 MHz; VDD = 1.8V; VDD_IO = 2.8V; VAA = 2.8V; VAA_PIX = 2.8V;

VDD_PLL = 2.8V; VDD_DAC = 2.8V; Default slew rate

Signal

Parameter

Conditions

Min

Typ

Max

Unit

EXTCLK

fextclk

max ±100 ppm

MHz

textclk_period

18.52

166.67

Duty cycle

PIXCLK1fpixclk

MHz

tpixclk_period

18.52

37.04

166.67

Duty cycle

DATA[7:0]

tpixclkf_dout

0.97

–

2.42

tdout_su

6.83

–

8.28

tdout_ho

2.74

–

6.32

FV/LV

tpixclkf_fvlv

1.15

–

2.53

tfvlv_su

6.72

–

8.1

tfvlv_ho

5.74

–

7.62

EXT CLK

PIXC LK

D OUT [7:0]

F R AM E_VALID

LIN E _VALID

pixclkf_dout

pixclkf_fvlv

Input

O utput

fvlv_su

fvlv_ho

dout_ho

dout_su

extclk_period

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