ASX340 datasheet(12/78 Pages) ETC2

12 / 78 page

PDF: 171981479/Source: 8304342517

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ASX340/MT9V139_DS Rev. C Pub. 3/11 EN

ASX340/MT9V139: 1/4-Inch Color CMOS NTSC/PAL Digital Image Sensor

Pin Descriptions and Assignments

Aptina Confidential and Proprietary

Preliminary

Pin Descriptions and Assignments

Table 4:

Pin Descriptions

Pin Number

Pin Name

Type

Description

Clock and Reset

EXTCLK

Input

Master input clock (27MHz): This can either be a square-wave generated from an

oscillator (in which case the XTAL input must be left unconnected) or connected

directly to a crystal.

XTAL

Output

If EXTCLK is connected to one pin of a crystal, this signal is connected to the other pin;

otherwise this signal must be left unconnected.

RESET_BAR

Input

Asynchronous active-low reset: When asserted, the device will return all interfaces to

their reset state. When released, the device will initiate the boot sequence. This signal

has an internal pull-up resistor.

FRAME_SYNC

Input

This input can be used to set the output timing of the ASX340/MT9V139 to a fixed

point in the frame.

The input buffer associated with this input is permanently enabled. This signal must

be connected to GND if not used.

SCLK

Input

These two signals implement serial communications protocol for access to the internal

registers and variables.

SDATA

Input/Output

SADDR

Input

This signal controls the device ID that will respond to serial communication

commands.

Two-wire serial interface device ID selection:

0: 0x90

1: 0xBA

SPI Interface

SPI_SCLK

Output

Clock output for interfacing to an external SPI memory such as Flash/EEPROM. Tristate

when RESET_BAR is asserted.

SPI_SDI

Input

Data in from SPI device. This signal has an internal pull-up resistor.

SPI_SDO

Output

Data out to SPI device. Tristate when RESET_BAR is asserted.

SPI_CS_N

Output

Chip selects to SPI device. Tristate when RESET_BAR is asserted.

(Parallel) Pixel Data Output

FRAME_VALID

Input/Output

Pixel data from the ASX340/MT9V139 can be routed out on this interface and

processed externally.

To save power, these signals are driven to a constant logic level unless the parallel pixel

data output or alternate (GPIO) function is enabled for these pins. For more

information see Table 16 on page 33.

This interface is disabled by default.

The slew rate of these outputs is programmable.

These signals can also be used as general purpose input/outputs.

LINE_VALID

Input/Output

PIXCLK

Output

F8, D6, D7,

C6, C7, B6,

B7, A6

DOUT[7:0]

Output

DOUT_LSB1

Input/Output

When the sensor core is running in bypass mode, it will generate 10 bits of output data

per pixel. These two pins make the two LSB of pixel data available externally. Leave

DOUT_LSB1 unconnected if not used. To save power, these signals are driven to a

constant logic level unless the sensor core is running in bypass mode or the alternate

function is enabled for these pins. For more information see Table 16,

“GPIO Bit Descriptions,” on page 38. The slew rate of these outputs is programmable.

DOUT_LSB0

Input/Output

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