STC89C53RC datasheet(90/165 Pages) STC

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TMOD register : Timer/Counter Mode Control Register

GATE

C/T

GATE

C/T

(MSB)

(LSB)

Timer 1

Timer 0

GATE

Gating control when set. Timer/Counter "x" is enabled only while "INTx " pin is high and

"TRx"control pin is set.When cleared Timer "x" is enabled whenever "TRx" control bit is set.

C/T

Timer or Counter Selector cleared for Timer operation (input from internal system clock). Set for

Counter operation (input from "Tx" input pin).

Operating Mode

B-bit Timer/Counter "THx" with "TLx" as 5-bit prescaler.

16-bit Timer/Counter"THx"and"TLx"are cascaded;there is no prescaler

8-bit auto-reload Timer/Counter “THx” holds a value which is to be reloaded into “TLx”

each time it overflows.

(Timer 0) TL0 is an 8-bit Timer/Counter controlled by the standard Timer 0 control bits

TH0 is an 8-bit timer only controlled by Timer 1 control bits.

(Timer 1) Timer/Counter 1 stopped

TCON register: Timer/Counter Control Register

TF1

TR1

TF0

TR0

IE1

IT1

IE0

IT0

(MSB)

(LSB)

Symbol

Position

Name and Significance

Symbol Position

Name and Significance

TF1

TCON.7 Timer 1 overflow Flag. Set by

hardware on Timer/Counter overflow.

cleared by hardware when processor

vectors to interrupt routine.

IE1

TCON.3 Interrupt 1 Edge flag. Set by

hardware when external interrupt

edge detected.Cleared when

interrupt processed.

TR1

TCON.6 Timer 1 Run control bit. Set/cleared

by software to turn Timer/Counter

on/off.

IT1

TCON.2 Intenupt 1 Type control bit. Set/

cleared by software to specify

falling edge/low level triggered

external interrupts.

TF0

TCON.5 Timer 0 overflow Flag. Set by

hardware on Timer/Counter overflow.

cleared by hardware when processor

vectors to interrupt routine.

IE0

TCON.1 Interrupt 0 Edge flag. Set by

hardware when external interrupt

edge detected.Cleared when

interrupt processed.

TR0

TCON.4 Timer 0 Run control bit. Set/cleared

by software to turn Timer/Counter

on/off.

IT0

TCON.0 Intenupt 0 Type control bit. Set/

cleared by software to specify

falling edge/low level triggered

external interrupts.

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