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STC89C53RC датащи(PDF) 17 Page - STCmicro Technology Co,.Ltd

номер детали STC89C53RC
подробное описание детали  Enhanced 80C51 Central Processing Unit ,6T or 12T per machine cycle
PDF  165 Pages
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производитель  STC [STCmicro Technology Co,.Ltd]
домашняя страница  http://www.stcmicro.com/
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2.2.2 Power-On Reset (POR)
When VCC drops below the detection threshold of POR circuit, all of the logic circuits are reset.
When VCC goes back up again, an internal reset is released automatically after a delay of 32768 clocks. The
nominal POR detection threshold is around 2.0V for 3V device and 3.3V for 5V device.
The Power-On flag, POF/PCON.4, is set by hardware to denote the VCC power has ever been less than the POR
voltage. And, it helps users to check if the start of running of the CPU is from power-on or from hardware reset
(RST-pin reset), software reset or Watchdog Timer reset. The POF bit should be cleared by software.
PCON register (Power Control Register)
LSB
bit
B7
B6
B5B4B3B2B1B0
name
SMOD SMOD0
-
POF
GF1
GF0
PD
IDL
POF
: Power-On flag. It is set by power-off-on action and can only cleared by software.
2.2.3 Watch-Dog-Timer
The watch dog timer in STC89xx series MCU consists of an 8-bit pre-scaler timer and an 15-bit timer. The timer
is one-time enabled by setting EN_WDT(WDT_CONTR.5). Clearing EN_WDT can stop WDT counting. When
the WDT is enabled, software should always reset the timer by writing 1 to CLR_WDT bit before the WDT
overflows. If STC89xx series MCU is out of control by any disturbance, that means the CPU can not run the
software normally, then WDT may miss the "writting 1 to CLR_WDT" and overflow will come. An overflow of
Watch-Dog-Timer will generate a internal reset.
1/256
1/128
1/64
1/32
1/16
1/8
1/4
1/2
8-bit prescalar
15-bit timer
-
-
EN_WDT CLR_WDT IDLE_WDT PS2 PS1 PS0
SYSclk/12
IDL/PCON.0
WDT_CONTR
WDT Structure
WDT_CONTR: Watch-Dog-Timer Control Register
LSB
bit
B7
B6
B5
B4
B3
B2B1B0
name
-
-
EN_WDT CLR_WDT IDLE_WDT PS2 PS1 PS0
17



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