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Chapter 4 Configurable I/O Ports Configurations

The STC89xx series MCU has following I/O ports: P0.0~P0.7, P1.0~P1.7, P2.0~P2.7, P3.0~P3.7, P4.0~P4.3(only

be available to LQFP44 and PLCC44). All port pins on STC89xx series may be independently configured to one

of four modes : quasi-bidirectional (standard 8051 port output), push-pull output, input-only or open-drain output

.All port pins default to quasi-bidirectional after reset. Each one has a Schmitt-triggered input for improved input

noise rejection.

4.1 Quasi-bidirectional I/O

Port pins in quasi-bidirectional output mode function similar to the standard 8051 port pins. A quasi-bidirectional

port can be used as an input and output without the need to reconfigure the port. This is possible because when

the port outputs a logic high, it is weakly driven, allowing an external device to pull the pin low. When the pin

outputs low, it is driven strongly and able to sink a large current. There are three pull-up transistors in the quasi-

bidirectional output that serve different purposes.

One of these pull-ups, called the “very weak” pull-up, is turned on whenever the port register for the pin contains

a logic “1”. This very weak pull-up sources a very small current that will pull the pin high if it is left floating.

A second pull-up, called the “weak” pull-up, is turned on when the port register for the pin contains a logic

“1” and the pin itself is also at a logic “1” level. This pull-up provides the primary source current for a quasi-

bidirectional pin that is outputting a 1. If this pin is pulled low by the external device, this weak pull-up turns off,

and only the very weak pull-up remains on. In order to pull the pin low under these conditions, the external device

has to sink enough current to over-power the weak pull-up and pull the port pin below its input threshold voltage.

The third pull-up is referred to as the “strong” pull-up. This pull-up is used to speed up low-to-high transitions on

a quasi-bidirectional port pin when the port register changes from a logic “0” to a logic “1”. When this occurs, the

strong pull-up turns on for two CPU clocks, quickly pulling the port pin high.

Vcc

2 clock

delay

Vcc

PORT

Weak

Very weak

Strong

PORT

LATCH DATA

INPUT

DATA

Quasi-bidirectional output

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