STC89C53RC datasheet(22/165 Pages) STC

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3.2 Data Memory

3.2.1 On-chip Scratch-Pad RAM

Just the same as the conventional 8051 micro-controller, there are 256 bytes of SRAM data memory including

128 bytes of SFR space available on the STC89xx series. The lower 128 bytes of data memory may be accessed

through both direct and indirect addressing. The upper 128 bytes of data memory and the 128 bytes of SFR

space share the same address space. The upper 128 bytes of data memory may only be accessed using indirect

addressing. The 128 bytes of SFR can only be accessed through direct addressing. The lowest 32 bytes (00H~1FH)

of data memory are grouped into 4 banks of 8 registers each. Program instructions call out these registers as R0

through R7. The RS0 and RS1 bits in PSW register(refer to section 3.2.4) select which register bank is in use.

Instructions using register addressing will only access the currently specified bank.This allows more efficient use

of code space, since register instructions are shorter than instructions that use direct addressing. The next 16 bytes

(20H~2FH) above the register banks form a block of bit-addressable memory space. The 80C51 instruction set

includes a wide selection of single-bit instructions, and the 128 bits in this area can be directly addressed by these

instructions. The bit addresses in this area are 00H through 7FH.

All of the bytes in the Lower 128 can be accessed by either direct or indirect addressing while the Upper 128

can only be accessed by indirect addressing. SFRs include the Port latches, timers, peripheral controls, etc.

These registers can only be accessed by direct addressing. Sixteen addresses in SFR space are both byte- and bit-

addressable. The bit-addressable SFRs are those whose address ends in 0H or 8H.

3.2.2 Auxiliary RAM

There are 1024 bytes of additional data RAM available on STC89C54RD+ series (while 256 bytes of additional

data RAM are available on STC89C51RC). They may be accessed by the instructions MOVX @Ri or MOVX

@DPTR. A control bit – EXTRAM located in AUXR.1 register (refer to section 3.2.4) is to control access of

auxiliary RAM. When set, disable the access of auxiliary RAM. When clear (EXTRAM=0), this auxiliary RAM

is the default target for the address range from 0x0000 to 0x03FF and can be indirectly accessed by move external

instruction, “MOVX @Ri” and “MOVX @DPTR”. If EXTRAM=0 and the target address is over 0x03FF,

switches to access external RAM automatically. When EXTRAM=0, the content in DPH is ignored when the

instruction MOVX @Ri is executed.

For KEIL-C51 compiler, to assign the variables to be located at Auxiliary RAM, the “pdata” or “xdata” definition

should be used. After being compiled, the variables declared by “pdata” and “xdata” will become the memories

accessed by “MOVX @Ri” and “MOVX @DPTR”, respectively. Thus the STC89xx series MCU hardware can

access them correctly.

3.2.3 External RAM

There is 64K-byte addressing space available for STC89xx series to access external data RAM. Just the same as

the design in the conventional 8051, the port – P2, P0, ALE, P3.6 and P3.7 have alterative function for external

data RAM access. To access the external data memory, the EXTRAM bit should be set to 1. Accesses to external

data memory can use either a 16-bit address (using ‘MOVX @DPTR’) or an 8-bit address (using ‘MOVX @Ri’).

8-bit addresses are often used in conjunction with one or more other I/O lines to page the RAM. If an 8-bit

address is being used, the contents of the Port 2 SFR remain at the Port 2 pins throughout the external memory

cycle. This will facilitate paging access. 16-bit addresses are often used to access up to 64K bytes of external data

memory.

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