STC89C53RC datasheet(88/165 Pages) STC

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6.6 Response Time

The INT0, INT1, INT2 and INT3 levels are inverted and latched into the interrupt flags IE0, IE1, IE2 and IE3 at

rising edge of every syetem clock cycle.

The Timer 0 and Timer 1 flags, TF0 and TF1, are set after which the timers overflow. The values are then polled

by the circuitry at rising edge of the next system clock cycle.

If a request is active and conditions are right for it to be acknowledged, a hardware subroutine call to the

requested service routine will be the next instruction to be executed. The call itself takes six system clock cycles.

Thus, a minimum of seven complete system clock cycles elapse between activation of an external interrupt

request and the beginning of execution of the first instruction of the service routine.

A longer response time would result if the request is blocked by one of the four previously listed conditions. If an

interrupt of equal or higher priority level is already in progress, the additional wait time obviously depends on the

nature of the other interrupt’s service routine. If the instruction in progress is not in its final cycle, the additional

wait time cannot be more than 3 cycles, since the longest instructions (LCALL) are only 6 cycles long, and if the

instruction in progress is RETI or an access to IE or IP, the additional wait time cannot be more than 5 cycles (a

maximum of one more cycle to complete the instruction in progress, plus 6 cycles to complete the next instruction

if the instruction is LCALL).

Thus, in a single-interrupt system, the response time is always more than 7 cycles and less than 12 cycles.

In the above assembly language solution, five distinct sections are the interrupt vector loactions, the main

program, and the three interrupt service routines. All vector loacations contain LJMP instructions to the respective

routines. The main program, starting at code address 0030H, contains only four instructions. SETB IT0 configures

the door sensing interrupt input as negative-edge triggered. MOV TMOD, #11H configures both timers for mode 1,

16-bit timer mode. Only the external 0 interrupt is enabled initially (MOV IE,#81H), so a "door-open" condition

is needed before any interrupt is accepted. Finally, SJMP $ puts the main program in a do-nothing loop.

When a door-open condition is sensed (by a high-to-low transition of INT0), an external 0 interrupt is

generated, INT0INT begins by putting the constant 20 in R7, then sets the overflow flags for both timers to force

timer interrupts to occur.

Timer interrupt will only occur, however, if the respective bits are enabled in the IE register. The next two

instructions (SETB ET0 and SETB ET1) enable timer interrupts. Finally, INT0INT terminates with a RETI to the

main program.

Timer 0 creates the 1 second timeout, and Timer 1 creates the 400Hz tone. After INT0INT returns to the main

program, timer interrupt are immediately generated (and accepted after one excution of SJMP $). Because of the

fixed polling sequence, the Timer 0 interrupt is serviced first. A 1 second timeout is created by programming 20

repetitions of a 50,000 us timeout. R7 serves as the counter. Nineteen times out of 20, T0INT operates as follows.

First, Timer 0 is turned off and R7 is decremented. Then, TH0/TL is reload with -50,000, the timer is turned back

on, and the interrupt is terminated. On the 20th Timer 0 interrupt, R7 is decremented to 0 (1 second has elapsed).

Both timer interrupts are disabled(CLR ET0, CLR ET1)and the interrupt is terminated. No further timer interrupts

will be generated until the next "door-open" condition is sensed.

The 400Hz tone is programmed using Timer 1 interrupts, 400Hz requires a period of 1/400 = 2,500 us or

1,250 high-time and 1,250 us low-time. Each timer 1 ISR simply puts -1250 in TH1/TL1, complements the port

bit driving the loudspeaker, then terminates.

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