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STC89C53RC датащи(PDF) 20 Page - STCmicro Technology Co,.Ltd

номер детали STC89C53RC
подробное описание детали  Enhanced 80C51 Central Processing Unit ,6T or 12T per machine cycle
PDF  165 Pages
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производитель  STC [STCmicro Technology Co,.Ltd]
домашняя страница  http://www.stcmicro.com/
Logo STC - STCmicro Technology Co,.Ltd

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2.2.4 Software RESET
Writing an “1” to SWRST bit in ISP_CONTR register will generate a internal reset.
ISP_CONTR: ISP/IAP Control Register
LSB
bit
B7
B6
B5
B4
B3
B2B1B0
name
ISPEN
SWBS
SWRST
-
-
WT2 WT1 WT0
ISPEN : ISP/IAP operation enable.
0 : Global disable all ISP/IAP program/erase/read function.
1 : Enable ISP/IAP program/erase/read function.
SWBS: software boot selection control.
0 : Boot from main-memory after reset.
1 : Boot from ISP memory after reset.
SWRST: software reset trigger control.
0 : No operation
1 : Generate software system reset. It will be cleared by hardware automatically.
B4 ~ B3: Reserved.
WT2~WT0 : ISP/IAP waiting time selection while flash is busy.
2.2.5 MAX810 power-on-reset delay
There is another on-chip POR delay circuit is integrated on STC89xx. This circuit is MAX810—sepcial reset
circuit and is controlled by configuring flash Option Register. Very long POR delay time – around 400ms will be
generated by this circuit once it is enabled.
20



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