SCD1284 datasheet(52/176 Pages) INTEL

52 / 176 page

CD1284 — IEEE 1284-Compatible Parallel Interface Controller

Datasheet

Type 2

If there is no data in the FIFO when the timer expires and the NNDT service request is enabled in

the SRER, a receive exception service request is posted with status indicating the timeout

condition. This timeout is optional and is provided so that driver software can detect the possible

end of a block of data and allow its buffers to be flushed to the higher, operating system level. The

NNDT is posted only on the first occurrence of a timeout after the FIFO becomes empty. Also note

that the NNDT timer is not started if the last character removed from the FIFO was an exception

character, such as a break or parity error.

Figure 8 on page 53 shows the timer process evaluation performed by the MPU when the timer

reaches zero.

5.5.3

Receive Exceptions

Several conditions can cause the CD1284 to post the receive exception service request. If an

exception condition occurs, two bytes are placed in the receive FIFO. The first byte contains the

status indicating the type of error; the second byte contains the data.

Exception data is sent to the CPU one event at a time. That is, there is a separate service request for

each character received with special conditions. If, when an exception condition occurs the receive

FIFO contains good data, a good data receive service request is immediately posted upon receipt of

the bad data. This happens regardless of the number of characters in the FIFO and the programmed

threshold. This allows the CPU to remove the data in the FIFO ahead of the exception data so that

the CD1284 can post the service request for the error condition. Once the service-acknowledge

procedure for the good data is terminated, a new service request is posted for the exception data.

When the CPU acknowledges the receive exception service request, it first reads the RDSR to

determine the status and then to retrieve the data. Reading the data is optional: if the FIFO is not

read twice during the service routine, the CD1284 updates the internal FIFO pointers appropriately

and discards the second byte.

Note:

The CPU need not actually read any data from the FIFO during an exception service acknowledge

— the FIFO pointers are correctly updated at the end of the service routine, discarding both the

status and the data. In this way, the CPU must at least read the status or it is permanently lost.)

Another special case of exception data handling is received line break conditions. A line break is a

character with a start bit, ‘0’ data, and no parity or stop bit. In this case, a null (‘0’) character is

placed in the FIFO with the break condition indicated in the accompanying status, and a receive

exception service request is posted. However, regardless of the length of the break, only one

character is placed in the FIFO. Resumption of normal character reception causes new data to again

be placed in the FIFO.

SCD1284 датащи(PDF) 52 Page - Intel Corporation