SCD1284 datasheet(90/176 Pages) INTEL

90 / 176 page

CD1284 — IEEE 1284-Compatible Parallel Interface Controller

Datasheet

6.0

Programming

6.1

Overview

As shown in the register summary tables in Chapter 4.0, the CD1284 local CPU interface is made

up of a large array of registers. These registers control all aspects of device behavior; some affect

overall chip operations, and others affect only one channel. Fortunately, most of the registers are

only modified once, during initialization, and rarely modified during normal operation. The

purpose of this chapter is to discuss these aspects, as well as the methods of interacting with the

CD1284 for channel-service needs.

6.2

Initialization

To properly power-up a CD1284, several procedures must be completed. These include device

initialization, programming global functions, and setting channel-specific parameters. In most

cases, initialization routines are executed once; during the overall system boot-up. The following

sections discuss these steps in detail (see Figure 18 on page 92 for a flow-chart step outline).

6.2.1

Device Reset

The procedures that perform chip reset are normally executed after a power-up, system-wide reset.

The hardware reset control signal, RESET* causes the CD1284 to perform its own internal

initialization. If desired, the driver software can issue a full chip reset before chip initialization

begins. To accomplish this, use the following steps (see Figure 18 for a flow-chart step outline):

1. Wait for CCR (Channel Command register) to contain 0x00.

The contents of the CCR must be ‘0’ before a command is issued. This is required to ensure

that any currently executing command has completed before the new one is started. Since this

is probably the first command being written to the CD1284 after power-on initialization, the

CCR is likely to be ‘0’, but it is recommended to always check the CCR before writing in a

new command.

2. Set the CAR (Channel Access register) to one of the two serial channels (2 or 3).

This step is required when the parallel channel does not respond to any value written to the

CCR address (this register does not exist in the parallel channel).

3. Write hexadecimal 81 (x’81) to the Channel Command Register (CCR).

This command causes the CD1284 to perform an all-channel and global reset. It causes the

internal RISC processor to begin execution from its power-up reset location. The results are

the same as if the RESET* input is activated. All internal interface registers are cleared, the

FIFOs are flushed, and all channels are disabled.

The full-chip reset command is a special-case CCR operation. Normally, the commands issued

to the CCR affect only the channel selected by the CAR. In this case, the setting of the CAR is

insignificant, but must be set to channel 2 or 3. Unlike other commands issued to the CCR, the

global reset command does not use the clearing of the CCR. Instead, the GFRCR indicates that

the command is complete (see below).

4. Wait for the firmware revision code to be written into the GFRCR.

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