SCD1284 datasheet(42/176 Pages) INTEL

42 / 176 page

CD1284 — IEEE 1284-Compatible Parallel Interface Controller

Datasheet

Before a serial request for service of a particular type is posted, the MPU checks the current state of

the request output for that type. If it is inactive, indicating that no other CD1284 is driving that

level, a request can be posted; otherwise it waits. This guarantees that each CD1284 has an

opportunity to have a request type serviced when required. When the CPU acknowledges the

request, both CD1284s receive the acknowledge through SVCACK*. However, only the first

receives DGRANT*. If there is an active request of this type pending, the CD1284 takes the

acknowledge and drives its vector register (RIVR, TIVR, MIVR) onto the data bus.

If the first device does not have a request pending, it passes the DGRANT* input to the second

CD1284 through the DPASS* output. Assuming that the second device has an active request

pending, it takes the acknowledge and drives its Vector register onto the data bus.

As previously mentioned, the upper five bits of the LIVR reflects what the CPU loaded into them

during its initialization of the CD1284s. These bits are used as a unique chip identification number

so the CPU can determine which CD1284 responded to the service acknowledge. These five bits

can be set to binary ‘0’ in the LIVRs of the first CD1284, and to binary ‘1’ in those of the second.

The CPU is able to test the bit to determine which device responded. Some examples of service-

acknowledge software routines that show one way of performing this task are provided in Chapter

6.0.

The common service acknowledge described in Section 5.3.2.3 on page 39 is also usable in daisy-

chained environments. In this case, the common acknowledge is applied to all service-

acknowledge inputs in all devices of the chain. The daisy-grant ripples down the chain until the

requesting device receives the acknowledge.

Note:

If a CD1284 further down the chain is requesting service for a receiver and one up the chain is

requesting service for a transmitter, the transmit request is serviced first since it precedes the

receive requester. Thus, the Fair Share mechanism is not functional in this configuration.

Figure 6. CD1284 Daisy-Chain Connections

DPASS*

SVCACKR*

SVCACKT*

SVCACKM*

DGRANT*

DPASS*

SVCACKR*

SVCACKT*

SVCACKM*

DGRANT*

SVCREQR*

SVCREQT*

SVCREQM*

SVCREQR*

SVCREQT*

SVCREQM*

SVCACKP*

SVCREQP*

ADDRESS

DECODE

LOGIC

CYCLE

ERROR

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