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SCD1284 датащи(PDF) 46 Page - Intel Corporation

номер детали SCD1284
подробное описание детали  IEEE 1284-Compatible Parallel Interface Controller with Two High-Speed Asynchronous Serial Ports
PDF  176 Pages
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производитель  INTEL [Intel Corporation]
домашняя страница  http://www.intel.com
Logo INTEL - Intel Corporation

SCD1284 датащи(HTML) 46 Page - Intel Corporation

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CD1284 — IEEE 1284-Compatible Parallel Interface Controller
46
Datasheet
Figure 7. Interrupt Generation Logic (Continued)
A1284 signal
transition from low-
to-high, and
A1284(ODR[3]) = 1
nInit signal
transition from
low-to-high, and
nInit(ODR[2]) = 1
HstBsy signal
transition from low-
to-high, and
HstBsy(ODR[1]) = 1
HstClk signal
transition from low-
to-high, and
HstClk(ODR[0]) = 1
MANMD
(PCR[7])
SIGCH
(PCIER[4])
SIGCH
(PCISR[4])
Interface must be in COMPATIBLE MODE
when MANMD (PCR.7) is set or MANMD wil
have no affect
HstClk signal
transition from
high-to-low, and
HstClk(ZDR[0]) = 1
HstBsy signal
transition from high-
to-low, and
HstBsy(ZDR[1]) = 1
A1284 signal
transition from
high-to-low, and
A1284(ZDR[3]) = 1
nInit signal
transition from
high to low, and
nInit(ZDR[2]) = 1
Host has reversed the direction of the interface from ECP-
forward to ECP-reverse by driving nReverseRequest (nInit)
signal low.
Host has changed the direction of the interface from ECP-
reverse to ECP-forward by driving nReverseRequest
(nInit) signal high.
DIRCH
(PCISR[2])
EPPAW
(PCISR[3])
NINIT
(PCISR[0])
EPPAW
(PCIER[3])
EPP address received
on parallel port
nInit
(PCIER[0])
In Compatible mode, the
host has requested the
peripheral to re-initialize
itself (nInit went low).
INTEN
(PFCR[4])
PPORT
(PIR[6])
(PCISR[5])
NEGCH
(PCISR[4])
SIGCH
(PCISR[3])
EPPAW
(PCISR[2])
DIRCH
(PCISR[1])
IDREQ
(PCISR[0])
NINIT



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