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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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SCD1284 датащи(PDF) 47 Page - Intel Corporation |
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SCD1284 датащи(HTML) 47 Page - Intel Corporation |
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47 / 176 page  IEEE 1284-Compatible Parallel Interface Controller — CD1284 Datasheet 47 Figure 7. Interrupt Generation Logic (Continued) DataErr (PFSR[0]) OneChar (PFSR[1]) Timeout (PFSR[5]) PPort (PIR[6]) Pipeline (PIR[5]) DMAwrerr (DER[7]) (DMAACK* w/o DMAREQ*) DMArderr (DER[6]) (DMAACK* w/o DMAREQ*) Bufwrerr (DER[5]) (write to non-empty DMABUF) HR1wrerr (DER[3]) (write to non- empty HR1) HR1rderr (DER[2]) (Read from empty HR1)) HR2wrerr (DER[1]) (Write to non- empty HR2) PPireq (PIR[7]) IntEn (PFCR[4]) Pipeline (PIR[5]) OneChar (PFSR[1]) Timeout (PFSR[5]) Interface in forward direction, PFHR2 full, PFHR1 empty, and Timeout (PFSR[5]) is set. Stale (PFSR[3]) transitions from false to true and: DMA is disabled. DMA is enabled, but DMABUF is empty (else, a DMAREQ* is generated, then a timeout interrupt is generated when the DMABUF is empty and all DMA cycles are complete. SRP (SVRR[3]) ErrEn (PFCR[1]) DataErr (PFSR[0]) Bufrderr (DER[4]) (Read from empty DMABUF) HR2rderr (DER[0]) (Read from empty HR2) |
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