AD9528 datasheet(29/67 Pages) AD

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Data Sheet

AD9528

Rev. D | Page 29 of 67

PLL2 Loop Filter

The PLL2 loop filter requires the connection of an external

capacitor from LF2_CAP (Pin 14) to LDO_VCO (Pin 15). The

value of the external capacitor depends on the operating mode

and the desired phase noise performance. For example, a loop

bandwidth of approximately 500 kHz produces the lowest

integrated jitter. A lower bandwidth produces lower phase noise

at 1 MHz but increases the total integrated jitter

LDO

RZERO

CPOLE2

RPOLE2

CPOLE1

VTUNE

LF2_CAP

CHARGE PUMP

LDO_VCO

Figure 31. PLL2 Loop Filter

Table 22. PLL2 Loop Filter Programmable Values

(Register 0x0205)

RZERO

(Ω)

CPOLE1

(pF)

RPOLE2

(Ω)

CPOLE2 (pF)

LF2_CAP2 (pF)

3250

900

Fixed at 16

Typical at 1000

3000

450

N/A1

2750

300

N/A1

2500

225

N/A1

2250

N/A1

2100

N/A1

2000

N/A1

1850

N/A1

1 N/A means not applicable.

2 External loop filter capacitor.

VCO

The VCO is tunable from 3.450 GHz to 4.025 GHz. The VCO

operates off the VCO LDO supply. This LDO requires an

external compensation cap of 0.47 μF to ground. The VCO

requires calibration prior to use.

VCO Calibration

The AD9528 on-chip VCO must be manually calibrated to

ensure proper PLL2 operation over process, supply, and

temperature. VCO calibration requires a valid VCXO input

clock and applicable preprogrammed PLL1 and PLL2 register

values prior to issuing the VCO calibration to ensure a PLL2

phase lock condition.

In addition, the value of the VCO CAL feedback divider (see

Figure 30) must equal the combined divider values of both the

8-bit N2 divider and RF VCO divider (M1). For example, if the

N2 divide value is 10 and the M1 divide value is 3, the total

PLL2 multiplication value is 30 in normal operation, so the

VCO CAL divider value must be set to 30 prior to initiating a

VCO calibration. See the PLL2 Feedback Dividers section for

more details. When total PLL2 feedback divider value is 15, see

Figure 53 for the detailed procedure.

VCO calibration is initiated by transitioning the calibrate VCO

bit (Bit 0 of Register 0x0203) from 0 to 1 (this bit is not self

clearing). The setting can be performed as part of the initial

setup before executing the IO_UPDATE bit (Register 0x000F,

Bit 0 = 1). A readback bit, VCO calibration in progress

(Register 0x0509, Bit 0), indicates when a VCO calibration is in

progress by returning a logic true (that is, Bit 0 = 1), however

this bit is automatically cleared after the calibration is finished,

so it tells if the calibration started but did not finish. After

calibration, initiate a sync (see the Clock Distribution

Synchronization section). A sync occurs automatically after

calibration. See Figure 53 for the detailed procedure.

During power-up or reset, channels driven by the RF VCO

driver are automatically held in sync until the first VCO

calibration is finished. Therefore, none of those channel outputs

can occur until VCO calibration is complete.

Initiate a VCO calibration under the following conditions:

•

After changing the PLL2 N2 or M1 divider settings or after

a change in the PLL2 reference clock frequency. This

means that a VCO calibration must be initiated any time

that a PLL2 register or reference clock changes such that a

different VCO frequency is the result.

•

Whenever system calibration is desired. The VCO is

designed to operate properly over temperature extremes,

even when it is first calibrated at the opposite extreme.

However, a VCO calibration can be initiated at any time.

To calibrate using the 2× multiplier, the total feedback divide

must be >16. If the application requires the use of a feedback

divide value <16, see the following example:

For fVCXO = 122.88 MHz, fVCO = 3686.4 MHz, M1 = 3, N2 = 5,

and with the 2× multiplier enabled, the total feedback divider

value of 15 is less than the supported minimum for the

calibration divider. To calibrate, the 2× multiplier must be

disabled, and the calibration divider must be set to 30. After the

calibration is complete, the 2× multiplier is enabled and the PLL

acquires lock.

PLL2 Lock Time/VCO Calibration Time

The typical PLL2 lock time occurs within 5× the period of the

loop bandwidth, assuming a phase margin of 55°. It can take up

to 10× the period of the loop bandwidth for the PLL2 lock

detector circuit to show locked status. The typical PLL2 VCO

calibration time is 400,000 periods of the PLL2 PFD rate.

Calculate PLL2_TO in Figure 52 as

PLL2_TO = 10/LBWPLL2 + 400,000/fPFD_PLL2

where fPFD_PLL2 is the frequency of the PLL2 phase detector.

CLOCK DISTRIBUTION

The clock distribution consists of 14 individual channels

(OUT0 to OUT13). The input frequency source for each

channel output is selectable as either the PLL1 output, PLL2

output, or SYSREF. Each of the output channels also includes a

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