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AD9528

Data Sheet

Rev. D | Page 16 of 67

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

VDD

REFA

REF_SEL

REFB

LF1

VCXO_VT

NIC

VDD

VCXO_IN

NIC

LF2_CAP

LDO_VCO

VDD

NIC

VDD4

OUT4

VDD5

OUT5

VDD6

OUT6

VDD7

OUT7

VDD8

OUT8

VDD9

OUT9

NOTES

1. NIC = NOT INTERNALLY CONNECTED. THIS PIN CAN BE LEFT FLOATING.

2. THE EXPOSED PAD IS THE GROUND CONNECTION ON THE CHIP.

IT MUST BE SOLDERED TO THE ANALOG GROUND OF THE PCB TO ENSURE

PROPER FUNCTIONALITY AND HEAT DISSIPATION, NOISE, AND MECHANICAL

STRENGTH BENEFITS.

AD9528

TOP VIEW

(Not to Scale)

Figure 2. Pin Configuration

Table 21. Pin Function Descriptions

No.

Mnemonic

Type1

Description

VDD

3.3 V Supply for the PLL1 Input Section.

REFA

Reference Clock Input A. Along with REFA, this pin is the differential input for the PLL reference.

Alternatively, this pin can be programmed as a single-ended 3.3 V CMOS input.

REFA

Complementary Reference Clock Input A. Along with REFA, this pin is the differential input for the

PLL reference. Alternatively, this pin can be programmed as a single-ended 3.3 V CMOS input.

REF_SEL

Reference Input Select. The reference input selection function defaults to software control via

internal Register 0x010A, Bits[2:0]. When the REF_SEL pin is active, a logic low selects REFA and logic

high selects REFB.

REFB

Reference Clock Input B. Along with REFB, this pin is the differential input for the PLL reference.

Alternatively, this pin can be programmed as a single-ended 3.3 V CMOS input.

REFB

Complementary Reference Clock Input B. Along with REFB, this pin is the differential input for the PLL

reference. Alternatively, this pin can be programmed as a single-ended 3.3 V CMOS input.

LF1

PLL1 External Loop Filter.

VCXO_VT

VCXO Control Voltage. Connect this pin to the voltage control pin of the external VCXO.

NIC

Not Internally Connected. The pin can be left floating.

VDD

3.3 V Supply for the PLL2 Section.

VCXO_IN

PLL1 Oscillator Input. Along with VCXO_IN, this pin is the differential input for the PLL reference.

Alternatively, this pin can be programmed as a single-ended 3.3 V CMOS input.

VCXO_IN

Complementary PLL1 Oscillator Input. Along with VCXO_IN, this pin is the differential input for the

PLL reference. Alternatively, this pin can be programmed as a single-ended 3.3 V CMOS input.

NIC

Not Internally Connected. The pin can be left floating.

LF2_CAP

PLL2 External Loop Filter Capacitor Connection. Connect capacitor between this pin and the

LDO_VCO pin.

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