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AD9528 датащи(PDF) 19 Page - Analog Devices

номер детали AD9528
подробное описание детали  JESD204B Clock Generator with 14 LVDS/HSTL Outputs
PDF  67 Pages
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производитель  AD [Analog Devices]
домашняя страница  http://www.analog.com
Logo AD - Analog Devices

AD9528 датащи(HTML) 19 Page - Analog Devices

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Data Sheet
AD9528
Rev. D | Page 19 of 67
TYPICAL PERFORMANCE CHARACTERISTICS
fVCXO = 122.88 MHz, REFA differential at 122.88 MHz, fVCO = 3686.4 MHz, and doubler is off, unless otherwise noted. External PLL1 loop
filter component values are as follows: RZERO = 10 kΩ, CZERO = 1 μF, CPOLE = 200 pF. External PLL2 external capacitor CZERO = 1 nF. PLL1
charge pump = 5 μA and PLL2 charge pump = 805 μA.
0
5
10
15
20
25
30
35
40
50
250
450
650
850
1050
1250
OUTPUT FREQUENCY (MHz)
Figure 3. VDDx Current (Typical) vs. Output Frequency, HSTL Mode
0
5
10
15
20
25
30
35
50
250
450
650
850
1050
1250
OUTPUT FREQUENCY (MHz)
LVDS
LVDS BOOST
Figure 4. VDDx Current (Typical) vs. Output Frequency, LVDS Mode and
LVDS Boost Mode
0
0.5
1.0
1.5
OUTPUT FREQUENCY (MHz)
2.0
2.5
0
200
400
600
800
1000
1200
1400
Figure 5. Differential Voltage Swing vs. Output Frequency, HSTL Mode
0
0.2
0.4
1.2
1.0
0.8
0.6
OUTPUT FREQUENCY (MHz)
0
200
400
600
800
1000
1200
1400
LVDS
LVDS BOOST
Figure 6. Differential Voltage Swing vs. Output Frequency, LVDS Mode and
LVDS Boost Mode
40
42
44
46
48
50
52
54
56
58
60
0200
400
600
OUTPUT FREQUENCY (MHz)
800
1000
1200
1400
HSTL
LVDS
LVDS BOOST
Figure 7. Positive Duty Cycle vs. Output Frequency, HSTL, LVDS, and LVDS
Boost Modes
CH1 500mV
Ω
M1.25ns 20.0GS/s
A CH1
80.0mV
1
Figure 8. Output Waveform (Differential), HSTL at 122.88 MHz



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