AD9528 datasheet(52/67 Pages) AD

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AD9528

Data Sheet

Rev. D | Page 52 of 67

CONTROL REGISTER MAP BIT DESCRIPTIONS

SERIAL CONTROL PORT CONFIGURATION (REGISTER 0x0000 TO REGISTER 0x0001)

Table 37. SPI Configuration A (Register 0x0000)

Bits

Bit Name

Description

Soft reset (SPI only)

Device reset.

LSB first (SPI only)

Bit order for SPI port. This bit has no effect in I2C mode.

1 = least significant bit first.

0 (default) = most significant bit first.

Address ascension

(SPI only)

This bit controls whether the register address is automatically incremented during a multibyte transfer. This

bit has no effect in I2C mode.

1 = register addresses are automatically incremented in multibyte transfers.

0 (default) = register addresses are automatically decremented in multibyte transfers.

SDO active (SPI only)

Enables SPI port SDO pin. This bit has no effect in I2C mode.

1 = 4-wire mode (SDO pin enabled).

0 (default) = 3-wire mode.

[3:0]

These bits are mirrors of Bits[7:4] of this register. However, each pair of the following corresponding bits are

logically AND gated internally; therefore, set the bits to Logic 1 or Logic 0 together.

Bit 3 corresponds to Bit 4.

Bit 2 corresponds to Bit 5.

Bit 1 corresponds to Bit 6.

Bit 0 corresponds to Bit 7.

Table 38. SPI Configuration B (Register 0x0001)

Bits

Bit Name

Description

[7:6]

Reserved

Reserved.

Read buffer register

For buffered registers, this bit controls whether the value read from the serial port is from the actual (active)

registers or the buffered copy.

1 = reads buffered values that take effect on the next assertion of IO_UPDATE.

0 (default) = reads values currently applied to the internal logic of the device.

[4:3]

Reserved

Reserved.

Reset sans regmap

This bit resets the device while maintaining the current register settings.

1 = resets the device.

0 (default) = no action.

[1:0]

Reserved

Reserved.

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