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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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AD9528 датащи(PDF) 6 Page - Analog Devices |
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AD9528 датащи(HTML) 6 Page - Analog Devices |
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6 / 67 page  AD9528 Data Sheet Rev. D | Page 6 of 67 Parameter Min Typ Max Unit Test Conditions/Comments HSTL Mode, 9 mA 80 mW Single 9 mA HSTL output at 122.88 MHz, channel divider = 10 85 mW Single 9 mA HSTL output at 409.6 MHz, channel divider = 3 95 mW Single 9 mA HSTL output at 983.04 MHz, VCO divider = 5, channel divider = 1 125 mW Single 9 mA HSTL output at 1228.8 MHz, channel divider = 1 REFA Differential On 72 mW REFA and REFB running at 122.88 MHz, REF_SEL = REFB Single-Ended 72 mW REFA and REFB running at 122.88 MHz, REF_SEL = REFB SYSREF Generator Enabled 5 mW Single 3.5 mA LVDS output at 960 kHz Fine Delay On 1 mW Maximum delay setting INPUT CHARACTERISTICS—REFA, REFA, REFB, REFB, VCXO_IN, VCXO_IN, SYSREF_IN, AND SYSREF_IN Table 4. Parameter Min Typ Max Unit Test Conditions/Comments DIFFERENTIAL MODE Input Frequency Range 400 MHz Input Frequency Range (VCXO_IN) 1250 MHz For buffer mode Input Slew Rate (VCXO_IN) 500 V/µs Minimum limit imposed for jitter performance Common-Mode Internally Generated Input Voltage 0.6 0.7 0.8 V Input Common-Mode Range 0.4 1.4 V DC-coupled LVDS mode and HSTL mode supported Differential Input Voltage, Sensitivity Frequency < 250 MHz 200 mV p-p Can accommodate single-ended inputs via ac grounding of unused inputs; instantaneous voltage on either pin must not exceed 1.8 V dc Differential Input Voltage, Sensitivity Frequency > 250 MHz 250 mV p-p Can accommodate single-ended inputs via ac grounding of unused inputs; instantaneous voltage on either pin must not exceed 1.8 V dc Input Noise Sensitivity 5 mV Differential Input Resistance 4.8 kΩ Differential Input Capacitance 4 pF Duty Cycle Duty cycle limits are set by pulse width high and pulse width low Pulse Width Low 1 ns Pulse Width High 1 ns CMOS MODE, SINGLE-ENDED INPUT Input Frequency Range 250 MHz Input High Voltage 1.4 V Input Low Voltage 0.65 V Input Capacitance 2 pF Duty Cycle Duty cycle limits are set by pulse width high and pulse width low Pulse Width Low 1.6 ns Pulse Width High 1.6 ns PLL1 CHARACTERISTICS Table 5. Parameter Min Typ Max Unit Test Conditions/Comments PFD FREQUENCY 110 MHz Charge Pump Current LSB Size 0.5 μA 7-bit resolution Reference Frequency Detector Threshold 950 kHz Do not use automatic holdover if the reference frequency is less than the minimum value |
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