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Data Sheet

AD9528

Rev. D | Page 25 of 67

THEORY OF OPERATION

DETAILED BLOCK DIAGRAM

CHARGE

PUMP

SYNC

VCXO

SWITCH-

OVER

CONTROL

OUT0

CONTROL

INTERFACE

(SDI AND I2C)

STATUS MONITOR

LOCK DETECT/

SERIAL PORT

ADDRESS

SCLK/SCL

SDO

SDIO/SDA

PLL 2

LOOP

FILTER

FINE

DELAY

SYNC

LOOP

FILTER

CHARGE

PUMP

PLL1

SYSREF GENERATION

SPI_SYS_REF

REQUEST

LOCK

DETECT

LOCK

DETECT

SYSREF

GENERATION

TRIGGER

REFA

REFB

AD9528

REF_SEL

STATUS0/SP0

LF2_CAP

VCXO_VT

VCXO_IN

RESET

10-BIT

DIVIDER

10-BIT

DIVIDER

5-BIT

DIVIDER

LF1

LDO_VCO

VCO

STATUS1/SP1

SYSREF_REQ

×2

DIVIDER

÷3, ÷4, ÷5

PLL2 FEEDBACK

DIVIDER = N2 (N3)

8-BIT DIVIDER

WITH COARSE

DELAY

8-BIT

DIVIDER

D Q

SYSREF_IN

OUT1

FINE

DELAY

SYNC

OUT2 TO OUT11

8-BIT DIVIDER

WITH COARSE

DELAY

D Q

OUT12

FINE

DELAY

SYNC

8-BIT DIVIDER

WITH COARSE

DELAY

D Q

OUT13

FINE

DELAY

SYNC

8-BIT DIVIDER

WITH COARSE

DELAY

D Q

10-BIT

DIVIDER

Figure 27. Top Level Diagram

OVERVIEW

The AD9528 is a clock generator that employs integer-N based

phase-locked loops (PLL). The device architecture consists of

two cascaded PLL stages. PLL1 consists of an integer division

PLL that uses an external voltage controlled crystal oscillator

(VCXO). PLL1 has a narrow loop bandwidth that provides

initial jitter cleanup of the input reference signal for the input

stage of PLL2. Conversely, the output of PLL1 is also routable to

any clock distribution output, if desired.

PLL2 is a frequency multiplying PLL that translates the first PLL

stage output frequency to a range of 3.450 GHz to 4.025 GHz.

PLL2 incorporates an integer based feedback divider that

enables integer frequency multiplication. An RF VCO divider

(3, 4, or 5) divides the VCO output of PLL2 before being routed

to the input of the clock distribution section. Programmable

integer dividers (1 to 256) in the clock distribution follow the

RF VCO divider, establishing a final output frequency up to

1 GHz or less for the 8 available outputs. The OUT0 to OUT3,

OUT12, and OUT13 outputs can run up to 1.25 GHz.

All of the divider settings in the clock distribution section are

configurable via the serial programming port, enabling a wide

range of input/output frequency ratios under program control.

The dividers also include a programmable coarse delay to adjust

timing of the output signals, if required. In addition, a fine delay

adjust is available in the clock distribution path.

The outputs are compatible with LVDS and HSTL logic levels.

The AD9528 can produce a JESD204B SYSREF signal. This

signal can be routed to any of the 14 outputs. The AD9528 can

also receive an externally generated SYSREF signal and buffer to

the outputs, with or without retiming. The AD9528 operates

over the extended industrial temperature range of −40°C to +85°C.

The AD9528 includes reference monitoring and automatic/manual

switchover and holdover. A reference select pin is available to

manually select which input reference is active. The accuracy of

the holdover is dependent on the external VCXO frequency

stability.

All power supply pins on the AD9528 operate on a 3.3 V ±5%

supply domain. However, each power supply pin has a dedicated

internal LDO regulator that provides approximately 1.8 V for

standard operation of the device. These independent regulators

provide extra supply rejection and help with output to output

coupling, since none of the output drivers or dividers share a

supply.

COMPONENT BLOCKS—PLL1

PLL1 General Description

PLL1 consists of a phase/frequency detector (PFD), a charge

pump, an external VCXO, and a partially external loop filter

operating in a closed loop.

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