LPC81XM datasheet(10/78 Pages) NXP

10 / 78 page

LPC81XM

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 4.6 — 4 April 2018

10 of 78

NXP Semiconductors

LPC81xM

32-bit ARM Cortex-M0+ microcontroller

[1]

Pin state at reset for default function: I = Input; AI = Analog Input; O = Output; PU = internal pull-up enabled (pins pulled up to full VDD

level); IA = inactive, no pull-up/down enabled.

[2]

5 V tolerant pad providing digital I/O functions with configurable pull-up/pull-down resistors and configurable hysteresis; includes

high-current output driver.

[3]

True open-drain pin. I2C-bus pins compliant with the I2C-bus specification for I2C standard mode, I2C Fast-mode, and I2C Fast-mode

Plus. Do not use this pad for high-speed applications such as SPI or USART. The pin requires an external pull-up to provide output

functionality. When power is switched off, this pin is floating and does not disturb the I2C lines. Open-drain configuration applies to all

functions on this pin.

Remark: If this pin is not available on the package, prevent it from internally floating as follows: Set bits 10 and 11 in the GPIO DIR0

register to 1 to enable the output driver and write 1 to bits 10 and 11 in the GPIO CLR0 register to drive the outputs LOW internally.

[4]

See Figure 11 for the reset pad configuration. RESET functionality is not available in Deep power-down mode. Use the WAKEUP pin to

reset the chip and wake up from Deep power-down mode. An external pull-up resistor is required on this pin for the Deep power-down

mode.

[5]

5 V tolerant pin providing standard digital I/O functions with configurable modes, configurable hysteresis, and analog input. When

configured as an analog input, the digital section of the pin is disabled, and the pin is not 5 V tolerant.

[6]

5 V tolerant pad providing digital I/O functions with configurable pull-up/pull-down resistors and configurable hysteresis. In Deep

power-down mode, pulling this pin LOW wakes up the chip. The wake-up pin function can be disabled and the pin can be used for other

purposes, if the WKT low power oscillator is enabled for waking up the part from Deep power-down mode.

[7]

5 V tolerant pad providing digital I/O functions with configurable pull-up/pull-down resistors and configurable hysteresis.

[8]

5 V tolerant pin providing standard digital I/O functions with configurable modes, configurable hysteresis, and analog I/O for the system

oscillator. When configured as an analog I/O, the digital section of the pin is disabled, and the pin is not 5 V tolerant.

[9]

The digital part of this pin is 3 V tolerant pin due to special analog functionality. Pin provides standard digital I/O functions with

configurable modes, configurable hysteresis, and an analog input. When configured as an analog input, the digital section of the pin is

disabled.

PIO0_12

[2] I/O

I; PU

PIO0_12 — General purpose digital input/output pin. ISP

entry pin on the SO20/TSSOP20/TSSOP16/XSON16

packages starting with chip version 4C (see Table 6). A

LOW level on this pin during reset starts the ISP command

handler.

See pin PIO0_1 for the DIP8 package and chip versions 1A

and 2A.

PIO0_13

[2] I/O

I; PU

PIO0_13 — General purpose digital input/output pin.

PIO0_14

[7] I/O

I; PU

PIO0_14 — General purpose digital input/output pin.

PIO0_15

[7] I/O

I; PU

PIO0_15 — General purpose digital input/output pin.

PIO0_16

[7] I/O

I; PU

PIO0_16 — General purpose digital input/output pin.

PIO0_17

[7] I/O

I; PU

PIO0_17 — General purpose digital input/output pin.

VDD

3.3 V supply voltage.

VSS

Ground.

Table 4.

Pin description table (fixed pins)

Symbol

Type Reset

state

[1]

Description

Table 5.

Movable functions (assign to pins PIO0_0 to PIO_17 through switch matrix)

Function name

Type

Description

U0_TXD

Transmitter output for USART0.

U0_RXD

Receiver input for USART0.

U0_RTS

Request To Send output for USART0.

U0_CTS

Clear To Send input for USART0.

LPC81xM датащи(PDF) 10 Page - NXP Semiconductors

LPC81xM датащи(HTML) 10 Page - NXP Semiconductors

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78

датащи скачать

ссылки URL