T48C893 datasheet(55/82 Pages) ATMEL

55 / 82 page

T48C893

Rev. A4, 22-Jan-02

55 (82)

8-bit Synchronous Mode

DATA

13823

SD/TO2

101

Bit 7

Bit 0

101

Bit 7

Bit 0

Data: 00110101

(rising edge)

(falling edge)

Figure 59. 8-bit synchronous mode

In the 8-bit synchronous mode, the SSI can operate as

either a 2- or 3-wire interface (see SSI peripheral

configuration). The serial data (SD) is received or

transmitted in NRZ format, synchronised to either the

rising or falling edge of the shift clock (SC). The choice

of clock edge is defined by the Serial Mode Control bits

(SM0,SM1). It should be noted that the transmission edge

refers to the SC clock edge with which the SD changes.

To avoid clock skew problems, the incoming serial input

data is shifted in with the opposite edge.

When used together with one of the timer modulator or

demodulator stages, the SSI must be set in the 8-bit

synchronous mode 1.

In RX mode, as soon as the SSI is activated (SIR= 0), 8

shift clocks are generated and the incoming serial data is

shifted into the shift register. This first telegram is

automatically transferred into the receive buffer and the

SRDY set to 0 indicating that the receive buffer contains

valid data. At the same time an interrupt (if enabled) is

generated. The SSI then continues shifting in the

following 8-bit telegram. If, during this time the first

telegram has been read by the controller, the second

telegram will also be transferred in the same way into the

receive buffer and the SSI will continue clocking in the

next telegram. Should, however, the first telegram not

have been read

(SRDY=1), then the SSI will stop,

temporarily holding the second telegram in the shift

is able to service the receive buffer. In this way no data is

lost or overwritten.

Deactivating the SSI (SIR=1) in mid–telegram will

immediately stop the shift clock and latch the present

contents of the shift register into the receive buffer. This

can be used for clocking in a data telegram of less than 8

bits in length. Care should be taken to read out the final

complete 8-bit data telegram of a multiple word message

before deactivating the SSI (SIR=1) and terminating the

reception. After termination, the shift register contents

will overwrite the receive buffer.

76 5 4 321

76543 2107654 321

msb

lsb

tx data 1

tx data 2

tx data 3

msb

lsb msb

lsb

Write STB

(tx data 2)

Write STB

(tx data 3)

Write STB

(tx data 1)

SIR

SRDY

Interrupt

(IFN = 0)

Interrupt

(IFN = 1)

ACT

13824

Figure 60. Example of 8-bit synchronous transmit operation

T48C893 датащи(PDF) 55 Page - ATMEL Corporation

T48C893 датащи(HTML) 55 Page - ATMEL Corporation

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82

датащи скачать

ссылки URL