T48C893 datasheet(30/82 Pages) ATMEL

30 / 82 page

T48C893

Rev. A4, 22-Jan-02

30 (82)

4.3.1

Timer 1

The Timer 1 is an interval timer which can be used to gen-

erate periodical interrupts and as prescaler for Timer 2,

Timer 3, the serial interface and the watchdog function.

The Timer 1 consists of a programmable 14-stage divider

that is driven by either SUBCL or SYSCL. The timer

output signal can be used as prescaler clock or as SUBCL

and as source for the Timer 1 interrupt. Because of other

system requirements the Timer 1 output T1OUT is

synchronized with SYSCL. Therefore in the power-down

mode SLEEP (CPU core –> sleep and OSC-Stop –> yes)

the output T1OUT is stopped (T1OUT=0). Nevertheless

the Timer 1 can be active in SLEEP and generate Timer 1

interrupts. The interrupt is maskable via the T1IM bit and

the SUBCL can be bypassed via the T1BP bit of the T1C2

programmed via the Timer 1 control register T1C1.

This timer starts running automatically after any

power-on reset ! If the watchdog function is not activated,

the timer can be restarted by writing into the T1C1

Timer 1 can also be used as a watchdog timer to prevent

a system from stalling. The watchdog timer is a 3-bit

counter that is supplied by a separate output of Timer 1.

It generates a system reset when the 3-bit counter

overflows. To avoid this, the 3-bit counter must be reset

before it overflows. The application software has to

accomplish this by reading the CWD register.

After power-on reset the watchdog must be activated by

software in the $RESET initialization routine. There are

two watchdog modes, in one mode the watchdog can be

switched on and off by software, in the other mode the

watchdog is active and locked. This mode can only be

stopped by carrying out a system reset.

The watchdog timer operation mode and the time interval

for the watchdog reset can be programmed via the

watchdog control register (WDC).

13766

Prescaler

14 bit

CL1

Watchdog

4 bit

MUX

WDCL

T1IM

T1BP

T1MUX

NRST

INT2

T1OUT

T1CS

SYSCL

SUBCL

Figure 28. Timer 1 module

Q1 Q2 Q3 Q4

Q11

Q14

RES

Decoder

Watchdog

mode control

MUX for interval timer

Decoder

MUX for watchdog timer

T1RM T1C2 T1C1 T1C0

WDL WDR WDT1 WDT0

WDC

RES

T1MUX

SUBCL

T1BP T1IM

T1IM=0

T1IM=1

INT2

T1OUT

T1C2

RESET

(NRST)

Watchdog

Divider / 8

Divider

RESET

T1C1

Write of the

T1C1 register

CL1

13767

WDCL

Read of the

CWD register

Figure 29. Timer 1 and watchdog

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