T48C893 datasheet(23/82 Pages) ATMEL

23 / 82 page

T48C893

Rev. A4, 22-Jan-02

23 (82)

4.2

Bidirectional Ports

With the exception of Port 1 and Port 6, all other ports (2,

4 and 5) are 4 bits wide. Port 1 and Port 6 have a data width

of 2 bits (bit 0 and bit 3). All ports may be used for data

input or output. All ports are equipped with Schmitt trig-

ger inputs and a variety of mask options for open drain,

open source, full complementary outputs, pull up and pull

down transistors. All Port Data Registers (PxDAT) are I/O

mapped to the primary address register of the respective

port address and the Port Control Register (PxCR), to the

corresponding auxiliary register.

There are five different directional ports available:

Port 1

2-bit wide bidirectional ports with automatic full

bus width direction switching.

Port 2

4-bit wide bitwise-programmable I/O port.

Port 5

4-bit wide bitwise-programmable bidirectional

port with optional strong pull-ups and program-

mable interrupt logic.

Port 4

4-bit wide bitwise-programmable bidirectional

port also provides the I/O interface to Timer 2,

SSI, voltage monitor input and external interrupt

input.

Port 6

2-bit wide bitwise-programmable bidirectional

port also provides the I/O interface to Timer 3

and external interrupt input.

4.2.1

Bidirectional Port 1

In Port 1 the data direction register is not independently

software programmable, the direction of the complete

port

being

switched

automatically when an I/O

instruction occurs (see figure 22). The port is switched to

output mode via an OUT instruction and to input via an

IN instruction. The data written to a port will be stored

into the output data latches and appears immediately at

the port pin following the OUT instruction. After RESET

all output latches are set to ’1’ and the port is switched to

input mode. An IN instruction reads the condition of the

associated pins.

Note:

Care must be taken when switching the bidirectional port

from output to input. The capacitive pin loading at this

port in conjunction with the high resistance pull-ups may

cause the CPU to read the contents of the output data

one should use either of the following programming

techniques:

Use two IN-instructions and DROP the first data

nibble. The first IN switches the port from output

to input and the DROP removes the first invalid

nibble. The second IN reads the valid pin state.

Use an OUT-instruction followed by an IN–

instruction.

Via

the

OUT-instruction,

the

capacitive load is charged or discharged depend-

ing

on the optional pull-up / pull-down

configuration. Write a ”1” for pins with pull-up

resistors and a ”0” for pins with pull-down

resistors.

OUT

Reset

I/O Bus

Master reset

P1DATy

(Data out)

(Direction)

BP1y

VDD

Switched

*) Mask options

VDD

Static

pull-up

Static

pull-down

pull-up

pull–down

Figure 22. Bidirectional Port 1

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