T48C893 datasheet(43/82 Pages) ATMEL

43 / 82 page

T48C893

Rev. A4, 22-Jan-02

43 (82)

8-bit comparator

Compare register 1

RES

Capture register

8-bit counter

13809

Compare register 2

Control

C31

C32

Control

T3SM1

T3RM1

T3IM1

T3TM1

TOG2

T3I

T3TM2

T3IM2

T3RM2

T3SM2

CL3

T3EIM

TOG3

INT5

CM31

CM32

: T3M1

: T3M2

Figure 45. Counter 3 stage

Timer / Counter Modes

Timer 3 has 6 timer modes and 6 modulator/demodulator

modes. The mode is set via the Timer 3 Mode Register

T3M.

In all these modes, the compare register and the compare-

mode register belonging to it define the counter value for

a compare match and the action of a compare match. A

match of the current counter value with the content of one

compare register triggers a counter reset, a Timer 3

interrupt or the toggling of the output flip-flop. The

compare mode registers T3M1 and T3M2 contain the

mask bits for enabling or disabling these actions.

The counter can also be enabled to execute single actions

with one or both compare registers. If this mode is set the

corresponding compare match event is generated only

once after the counter start.

Most of the timer modes use its compare registers

alternately. After the start has been activated, the first

comparison is carried out via the compare register 1,

the second is carried out via the compare register 2, the

third is carried out again via the compare register 1

and so on. This makes it easy to generate signals with

constant periods and variable duty cycle or to generate

signals with variable pulse and space widths.

If single-action mode is set for one compare register, the

comparison is always carried out after the first cycle via

the other compare register.

The counter can be started and stopped via the control

of the output before start. T3C contains the interrupt mask

for a T3I input interrupt.

Via the Timer 3 clock-select register, the internal or

external clock source can be selected. This register selects

also the active edge of the external input. An edge at the

external input T3I can generate also an interrupt if the

T3EIM-bit is set and the Timer 3 is stopped (T3R = 0) in

the T3C-register.

The status of the timer as well as the occurrence of a

compare match or an edge detect of the input signal is

indicated by the status register T2ST. This allows

identification of the interrupt source because all these

events share only one timer interrupt.

Timer 3 compare data values

The Timer 3 has two 8-bit compare registers (T3CO1,

T3CO2). The compare data value can be ‘m’ for each of

the Timer 3 compare registers.

The compare data value for the compare registers is:

m = x +1

≤ x ≤ 255

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