T48C893 datasheet(31/82 Pages) ATMEL

31 / 82 page

T48C893

Rev. A4, 22-Jan-02

31 (82)

Timer 1 Control Register 1 (T1C1)

Address: ’7’hex – Subaddress: ’8’hex

Bit 3 *

Bit 2

Bit 1

Bit 0

T1C1

T1RM

T1C2

T1C1

T1C0

Reset value: 1111b

* Bit 3 –> MSB, Bit 0 –> LSB

T1RM

Timer 1 Restart Mode

T1RM = 0, write access without Timer 1 restart

T1RM = 1, write access with Timer 1 restart

Note: if WDL = 0, Timer 1 restart is impossible

T1C2

Timer 1 Control bit 2

T1C1

Timer 1 Control bit 1

T1C0

Timer 1 Control bit 0

The three bits T1C[2:0] select the divider for timer 1. The

resulting time interval depends on this divider and the

timer 1 input clock source. The timer input can be sup-

plied by the system clock, the 32kHz oscillator or via the

clock management. If the clock management generates

the SUBCL, the selected input clock from the RC oscilla-

tor, 4MHz oscillator or an external clock is divided by 16.

T1C2

T1C1

T1C0

Divider

Time Interval with

SUBCL

Time Interval with

SUBCL = 32 kHz

Time Interval with

SYSCL = 2/1 MHz

SUBCL / 2

µs

µs / 2 µs

SUBCL / 4

122

µs

µs / 4 µs

SUBCL / 8

244

µs

µs / 8 µs

SUBCL / 16

488

µs

µs / 16 µs

SUBCL / 32

0.977 ms

µs / 32 µs

256

SUBCL / 256

7.812 ms

128

µs / 256 µs

2048

SUBCL / 2048

62.5 ms

1024

µs / 2048 µs

16384

SUBCL / 16384

500 ms

8192

µs / 16384 µs

Timer 1 Control Register 2 (T1C2)

Address: ’7’hex – Subaddress: ’9’hex

Bit 3 *

Bit 2

Bit 1

Bit 0

T1C2

– – –

T1BP

T1CS

T1IM

Reset value: x111b

* Bit 3 –> MSB, Bit 0 –> LSB

T1BP

Timer 1 SUBCL ByPassed

T1BP = 1, TIOUT = T1MUX

T1BP = 0, T1OUT = SUBCL

T1CS

Timer 1 input Clock Select

T1CS = 1, CL1 = SUBCL (see figure 28)

T1CS = 0, CL1 = SYSCL (see figure 28)

T1IM

Timer 1 Interrupt Mask

T1IM = 1, disables Timer 1 interrupt

T1IM = 0, enables Timer 1 interrupt

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