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T48C893 датащи(PDF) 26 Page - ATMEL Corporation |
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T48C893 датащи(HTML) 26 Page - ATMEL Corporation |
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26 / 82 page ![]() T48C893 Rev. A4, 22-Jan-02 26 (82) Port 5 Data Register (P5DAT) Primary register address: ’5’hex Bit 3 Bit 2 Bit 1 Bit 0 P5DAT P5DAT3 P5DAT2 P5DAT1 P5DAT0 Reset value: 1111b Port 5 Control Register (P5CR) Byte Write Auxiliary register address: ’5’hex Bit 3 Bit 2 Bit 1 Bit 0 P5CR First write cycle P51M2 P51M1 P50M2 P50M1 Reset value: 1111b Bit 7 Bit 6 Bit 5 Bit 4 Second write cycle P53M2 P53M1 P52M2 P52M1 Reset value: 1111b P5xM2, P5xM1 – Port 5x Interrupt mode/direction code Auxiliary Address: ’5’hex First Write Cycle Second Write Cycle Code 3 2 1 0 Function Code 3 2 1 0 Function x x 1 1 BP50 in input mode – interrupt disabled x x 1 1 BP52 in input mode – interrupt disabled x x 0 1 BP50 in input mode – rising edge interrupt x x 0 1 BP52 in input mode – rising edge interrupt x x 1 0 BP50 in input mode – falling edge interrupt x x 1 0 BP52 in input mode – falling edge interrupt x x 0 0 BP50 in output mode – interrupt disabled x x 0 0 BP52 in output mode – interrupt disabled 1 1 x x BP51 in input mode – interrupt disabled 1 1 x x BP53 in input mode – interrupt disabled 0 1 x x BP51 in input mode – rising edge interrupt 0 1 x x BP53 in input mode – rising edge interrupt 1 0 x x BP51 in input mode – falling edge interrupt 1 0 x x BP53 in input mode – falling edge interrupt 0 0 x x BP51 in output mode – interrupt disabled 0 0 x x BP53 in output mode – interrupt disabled |
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