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T48C893 датащи(PDF) 52 Page - ATMEL Corporation |
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T48C893 датащи(HTML) 52 Page - ATMEL Corporation |
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52 / 82 page ![]() T48C893 Rev. A4, 22-Jan-02 52 (82) Timer 3 COmpare Register 1 (T3CO1) Byte Write Address: ’B’hex – Subaddress: ’4’hex High nibble T3CO1 Second write cycle Bit 7 Bit 6 Bit 5 Bit 4 Reset value: 1111b Low nibble First write cycle Bit 3 Bit 2 Bit 1 Bit 0 Reset value: 1111b Timer 3 COmpare Register 2 (T3CO2) Byte Write Address: ’B’hex – Subaddress: ’5’hex High nibble T3CO2 Second write cycle Bit 7 Bit 6 Bit 5 Bit 4 Reset value: 1111b Low nibble First write cycle Bit 3 Bit 2 Bit 1 Bit 0 Reset value: 1111b Timer 3 Capture register The counter content can be read via the capture register. There are two ways to use the capture register. In modes 1 and 4, it is possible to read the current counter value directly out of the capture register. In the capture modes 2, 3, 5 and 12, a capture event like an edge at the Timer 3 input or a signal from Timer 2 stores the current counter value into the capture register. This counter value can be read from the capture register. Timer 3 CaPture Register (T3CP) Byte Read Address: ’B’hex – Subaddress: ’4’hex High nibble T3CP First read cycle Bit 7 Bit 6 Bit 5 Bit 4 Reset value: xxxxb Low nibble Second read cycle Bit 3 Bit 2 Bit 1 Bit 0 Reset value: xxxxb |
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