SC68C752B datasheet(31/49 Pages) PHILIPS

31 / 49 page

SC68C752B_3

Product data sheet

Rev. 03 — 29 November 2005

31 of 49

Philips Semiconductors

SC68C752B

5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 64-byte FIFOs

Remark: TCR can only be written to when EFR[4] = 1 and MCR[6] = 1. The programmer

must program the TCR such that TCR[3:0] > TCR[7:4]. There is no built-in hardware

check to make sure this condition is met. Also, the TCR must be programmed with this

condition before Auto-RTS or software ﬂow control is enabled to avoid spurious operation

of the device.

7.13 Trigger Level Register (TLR)

This 8-bit register is pulsed to store the transmit and received FIFO trigger levels used for

DMA and interrupt generation. Trigger levels from 4 to 60 can be programmed with a

granularity of 4. Table 22 shows trigger level register bit settings.

Remark: TLR can only be written to when EFR[4] = 1 and MCR[6] = 1. If TLR[3:0] or

TLR[7:4] are logical 0, the selectable trigger levels via the FIFO control register (FCR) are

used for the transmit and receive FIFO trigger levels. Trigger levels from

4 bytes to 60 bytes are available with a granularity of four. The TLR should be

programmed for N

⁄

4, where N is the desired trigger level.

When the trigger level setting in TLR is zero, the SC68C752B uses the trigger level setting

deﬁned in FCR. If TLR has non-zero trigger level value, the trigger level deﬁned in FCR is

discarded. This applies to both transmit FIFO and receive FIFO trigger level setting.

When TLR is used for RX trigger level control, FCR[7:6] should be left at the default state,

that is, ‘00’.

7.14 FIFO ready register

The FIFO ready register provides real-time status of the transmit and receive FIFOs of

both channels.

The FIFO Rdy register is a read-only register that can be accessed when any of the two

UARTs is selected CS = 0, MCR[2] (FIFO Rdy Enable) is a logic 1, and loopback is

disabled. The address is 111.

Table 22:

Trigger Level Register bits description

Bit

Symbol

Description

7:4

TLR[7:4]

RX FIFO trigger levels (4 to 60), number of characters available.

3:0

TLR[3:0]

TX FIFO trigger levels (4 to 60), number of spaces available.

Table 23:

FIFO ready register bits description

Bit

Symbol

Description

7:6

FIFO Rdy[7:6]

unused; always 0

FIFO Rdy[5]

RX FIFO B status; related to DMA

FIFO Rdy[4]

RX FIFO A status; related to DMA

3:2

FIFO Rdy[3:2]

unused; always 0

FIFO Rdy[1]

TX FIFO B status; related to DMA

FIFO Rdy[0]

TX FIFO A status; related to DMA

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