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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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SC68C752B датащи(PDF) 21 Page - NXP Semiconductors |
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SC68C752B датащи(HTML) 21 Page - NXP Semiconductors |
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21 / 49 page  SC68C752B_3 © Koninklijke Philips Electronics N.V. 2005. All rights reserved. Product data sheet Rev. 03 — 29 November 2005 21 of 49 Philips Semiconductors SC68C752B 5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 64-byte FIFOs Table 11 lists and describes the SC68C752B internal registers. [1] These registers are accessible only when LCR[7] = 0. [2] This bit can only be modified if register bit EFR[4] is enabled, that is, if enhanced functions are enabled. [3] The Special register set is accessible only when LCR[7] is set to a logic 1. Table 11: SC68C752B internal registers A2 A1 A0 Register Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Read/ Write General register set [1] 0 0 0 RHR bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 R 0 0 0 THR bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 W 001IER CTS interrupt enable [2] RTS interrupt enable [2] Xoff [2] Sleep mode [2] modem status interrupt receive line status interrupt THR empty interrupt RX data available interrupt R/W 0 1 0 FCR RX trigger level (MSB) RX trigger level (LSB) TX trigger level (MSB) [2] TX trigger level (LSB) [2] DMA mode select TX FIFO reset RX FIFO reset FIFO enable W 0 1 0 IIR FCR[0] FCR[0] CTS, RTS Xoff interrupt priority bit 2 interrupt priority bit 1 interrupt priority bit 0 interrupt status R 0 1 1 LCR DLAB break control bit set parity parity type select parity enable number of stop bits word length bit 1 word length bit 0 R/W 1 0 0 MCR 1 × or 1 ×/4 clock [2] TCR and TLR enable [2] Xon Any [2] enable loopback OPA/ OPB control FIFO ready enable RTS DTR R/W 1 0 1 LSR error in RX FIFO THR and TSR empty THR empty break interrupt framing error parity error overrun error data in receiver R 1 1 0 MSR CD RI DSR CTS ∆CD ∆RI ∆DSR ∆CTS R 1 1 1 SPR bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 R/W 1 1 0 TCR bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 R/W 1 1 1 TLR bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 R/W 1 1 1 FIFO Rdy 0 0 RX FIFO B status RX FIFO A status 0 0 TX FIFO B status TX FIFO A status R Special register set [3] 0 0 0 DLL bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 R/W 0 0 1 DLH bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 R/W Enhanced register set [4] 0 1 0 EFR Auto CTS Auto RTS special character detect enable enhanced functions [2] software flow control bit 3 software flow control bit 2 software flow control bit 1 software flow control bit 0 R/W 1 0 0 XON1 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 R/W 1 0 1 XON2 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 R/W 1 1 0 XOFF1 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 R/W 1 1 1 XOFF2 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 R/W |
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