SC68C752B datasheet(8/49 Pages) PHILIPS

8 / 49 page

SC68C752B_3

Product data sheet

Rev. 03 — 29 November 2005

8 of 49

Philips Semiconductors

SC68C752B

5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 64-byte FIFOs

Functional description

The UART will perform serial-to-parallel conversion on data characters received from

peripheral devices or modems, and parallel-to-parallel conversion on data characters

transmitted by the processor. The complete status of each channel of the SC68C752B

UART can be read at any time during functional operation by the processor.

The SC68C752B can be placed in an alternate mode (FIFO mode) relieving the processor

of excessive software overhead by buffering received/transmitted characters. Both the

receiver and transmitter FIFOs can store up to 64 bytes (including three additional bits of

error status per byte for the receiver FIFO) and have selectable or programmable trigger

levels. Primary outputs RXRDY and TXRDY allow signalling of DMA transfers.

The SC68C752B has selectable hardware ﬂow control and software ﬂow control.

Hardware ﬂow control signiﬁcantly reduces software overhead and increases system

efﬁciency by automatically controlling serial data ﬂow using the RTS output and CTS input

signals. Software ﬂow control automatically controls data ﬂow by using programmable

Xon/Xoff characters.

The UART includes a programmable baud rate generator that can divide the timing

reference clock input by a divisor between 1 and (216

− 1).

6.1 Trigger levels

The SC68C752B provides independent selectable and programmable trigger levels for

both receiver and transmitter DMA and interrupt generation. After reset, both transmitter

and receiver FIFOs are disabled and so, in effect, the trigger level is the default value of

one byte. The selectable trigger levels are available via the FCR. The programmable

trigger levels are available via the Trigger Level Register (TLR).

6.2 Hardware ﬂow control

Hardware ﬂow control is comprised of Auto-CTS and Auto-RTS. Auto-CTS and Auto-RTS

can be enabled/disabled independently by programming EFR[7:6].

With Auto-CTS, CTS must be active before the UART can transmit data.

Auto-RTS only activates the RTS output when there is enough room in the FIFO to receive

data and de-activates the RTS output when the RX FIFO is sufﬁciently full. The halt and

resume trigger levels in the TCR determine the levels at which RTS is

activated/deactivated.

If both Auto-CTS and Auto-RTS are enabled, when RTS is connected to CTS, data

transmission does not occur unless the receiver FIFO has empty space. Thus, overrun

errors are eliminated during hardware ﬂow control. If not enabled, overrun errors occur if

the transmit data rate exceeds the receive FIFO servicing latency.

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