SC68C752B datasheet(25/49 Pages) PHILIPS

25 / 49 page

SC68C752B_3

Product data sheet

Rev. 03 — 29 November 2005

25 of 49

Philips Semiconductors

SC68C752B

5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 64-byte FIFOs

7.5 Line Status Register (LSR)

Table 14 shows the Line Status Register bit settings.

When the LSR is read, LSR[4:2] reﬂect the error bits (BI, FE, PE) of the character at the

top of the RX FIFO (next character to be read). The LSR[4:2] registers do not physically

exist, as the data read from the RX FIFO is output directly onto the output data bus,

D[4:2], when the LSR is read. Therefore, errors in a character are identiﬁed by reading the

LSR and then reading the RHR.

LSR[7] is set when there is an error anywhere in the RX FIFO, and is cleared only when

there are no more errors remaining in the FIFO.

Reading the LSR does not cause an increment of the RX FIFO read pointer. The RX FIFO

read pointer is incremented by reading the RHR.

Table 14:

Line Status Register bits description

Bit

Symbol

Description

LSR[7]

FIFO data error.

logic 0 = No error (normal default condition)

logic 1 = At least one parity error, framing error, or break indication is in the

receiver FIFO. This bit is cleared when no more errors are present in the

FIFO.

LSR[6]

THR and TSR empty. This bit is the Transmit Empty indicator.

logic 0 = transmitter hold and shift registers are not empty

logic 1 = transmitter hold and shift registers are empty

LSR[5]

THR empty. This bit is the Transmit Holding Register Empty indicator.

logic 0 = Transmit Hold Register is not empty

logic 1 = Transmit Hold Register is empty. The processor can now load up to

64 bytes of data into the THR if the TX FIFO is enabled.

LSR[4]

Break interrupt.

logic 0 = no break condition (normal default condition)

logic 1 = A break condition occurred and associated byte is 00, that is,

RX was LOW for one character time frame.

LSR[3]

Framing error.

logic 0 = no framing error in data being read from RX FIFO (normal default

condition)

logic 1 = Framing error occurred in data being read from RX FIFO, that is,

received data did not have a valid stop bit.

LSR[2]

Parity error.

logic 0 = no parity error (normal default condition)

logic 1 = parity error in data being read from RX FIFO

LSR[1]

Overrun error.

logic 0 = no overrun error (normal default condition)

logic 1 = overrun error has occurred

LSR[0]

Data in receiver.

logic 0 = no data in receive FIFO (normal default condition)

logic 1 = at least one character in the RX FIFO

SC68C752B датащи(PDF) 25 Page - NXP Semiconductors

SC68C752B датащи(HTML) 25 Page - NXP Semiconductors

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49

датащи скачать

ссылки URL