LTC6946 datasheet(38/54 Pages) LINER

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LTC2000A

2000afb

For more information www.linear.com/LTC2000A

APPLICATIONS INFORMATION

are synchronized the mismatch in the DAC output timing

will be limited to 30ps.

Once all the DAC sample clocks and LVDS data clocks are

aligned, determine whether any DACs are being updated

onecyclelate(suchasDACXinFigure15a)bydetermining

whether DCKIP/N is arriving at the DACs within the same

CKP/N clock cycle. To do this in dual-port mode, first use

the phase comparator outputs SYNC_PH and Table 12

to determine the delay from the DCKIP/N rising edge to

the next CKP/N rising edge for each DAC (measured in

sample clock cycles).

Recall that the DCKIP/N timing mismatch must be kept

below 0.4 cycles of the sample clock. If DCKIP/N ar-

rives at both DACs within the same sample clock cycle,

the difference in DCKIP/N to CKP/N delays indicated by

SYNC_PH will equal the actual DCKIP/N timing mismatch,

and thus will be less than 0.4 cycles. If DCKIP/N arrives

at the DACs within different cycles, as in Figure 15a, the

difference in the delays indicated by SYNC_PH will equal

1 cycle minus the actual DCKIP/N timing mismatch, and

thus will be greater than 0.4 cycles. Thus if the difference

between the delays indicated by SYNC_PH is greater than

CKP/N

DAC X

LTC2000A

DCKIP/N

LVDS DATA

LVDS CLK

MATCHED

DELAYS

MATCHED

DELAYS

DAP/N

DBP/N

CKP/N

DAC Y

LTC2000A

DCKIP/N

2000A F14

LVDS DATA

LVDS CLK

DAP/N

DBP/N

CLOCK

SOURCE

FPGA

DAP/N[15:0]

N+2

N+4

N+6

N+8

N+10

DBP/N[15:0]

DAC X

DCKIP/N

DAC X

IOUTP/N

DAC X

IOUTP/N

(ADJUSTED)

DAC Y

IOUTP/N

DAC Y

DCKIP/N

CKP/N

N+1

N+3

0.9

CYCLES

0.1 CYCLES

10 CYCLES

2000A F15a

N+5

N+7

N+9

N+11

N+1

9 CYCLES

10 CYCLES

Figure 14. System with Multiple LTC2000A DACs Synchronized

Figure 15a. Sample Waveforms — Synchronizing Multiple LTC2000As in Dual Port Mode

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