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LTC2000A

2000afb

For more information www.linear.com/LTC2000A

APPLICATIONS INFORMATION

10. Apply desired data pattern to ports A and B (DAP/N,

DBP/N) for dual-port mode, or only to port B for

single-port mode. Port A samples will precede port B

samples at the DAC output when using dual-port

mode.

Output Configurations

TheLTC2000A’scomplementarycurrentoutputs(IOUTP/N)

source current into an external load referenced to GND.

Outputloadconfiguration,componentselection,andlayout

are critical to the performance of the LTC2000A. For best

AC performance, the output stages should be configured

for differential (or balanced) operation.

A differential resistor loaded output is a very simple output

stage.WellmatchedresistorsareconnectedbetweenGND

and IOUTP/N, with the resistance values setting both the

output swing and non-zero output common-mode voltage

(Figure 9). While it is economical, this type of output stage

can drive only differential loads with impedance levels and

amplitudes appropriate for the DAC outputs.

Differential transformer-coupled output configurations

usually give the best AC performance and provide excel-

lent rejection of common mode distortion and noise over

a broad frequency range. Figure 10 shows a transformer

output configuration that uses a Mini-Circuits TC1-1-13M

and a JTX-2-10T RF transformer for differential to single-

ended conversion.

IOUTP

2000A F09

LTC2000A

IOUTN

Figure 9. Differential Resistor Output Load

Figure 10. Transformer-Based Output Configuration

for Differential to Single-Ended Conversion

IOUTP

2000A F10

LTC2000A

MINI-CIRCUITS

TC1-1-13M

MINI-CIRCUITS

JTX-2-10T

•

IOUTN

• •

For any output configuration, any imbalances in the output

impedance between the IOUTP and IOUTN pins results in

asymmetrical signal swings that lead to distortion (mostly

even order). Careful consideration is needed to select the

best output configuration for a given application.

Generating the DAC Sample Clock

For best AC performance, it is important that the DAC

sample clock waveforms be clean, with low phase noise

and good jitter performance, as the phase noise and spuri-

ous content of the clock source will appear directly in the

DAC output spectrum.

A differential clock should be AC coupled onto the CKP/N

pins, since the DC bias point of CKP/N is set internally to

1V through a 5k impedance. Figure 11 shows the DAC

sample clock receiver input and common-mode voltage

control. While the differential input voltage range of the

clock receiver spans from ±300mV to ±1.8V, a signal with

the highest possible slew rate and amplitude and a bal-

anced duty cycle is recommended. Traces that carry the

differential clock signal need to have accurately controlled

impedance and accurate termination as close to the CKP/N

pins of the LTC2000A as possible.

There are several ways to generate the DAC sample clock.

For lab evaluation and testing, a high quality RF signal

generator can provide a clean high frequency sine wave

that is converted to the DAC sample clock with a 1:1 RF

transformer or balun (see Figure 12).

Figure 11. DAC Sample Clock Receiver

AVDD18

LTC2000A

CKP

CKN

GND

2000A F11

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