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LTC2000A

2000afb

For more information www.linear.com/LTC2000A

OPERATION

Table 3. DAC Sample Clock, and Divided Clock Output SPI Registers

ADDRESS

BIT

NAME

DESCRIPTION

0x02

CK_PD

CKP/N Clock Receiver Power Down When CK_PD = 1

CK_OK

CKP/N Clock Present Indicator. When CK_OK = 1, clock is present at CKP/N pins and fDAC > 50MHz.

When CK_OK = 0, DAC output is forced to mid-scale. CK_OK is read only.

DCKO_DIS DCKOP/N Output Disable. Set DCKO_DIS = 1 to power down the DCKO LVDS transmitter. For DCKO_DIS = 1,

DCKOP/N are high impedance.

DCKO_DIV DCKOP/N Divide Select. When DCKO_DIV = 0, fDCKOP/N = fDAC/4. When DCKO_DIV = 1, fDCKOP/N = fDAC/2.

DCKO_ISEL DCKOP/N Output Current Select. When DCKO_ISEL = 0, output current is 3.5mA. When DCKO_ISEL = 1,

output current is 7mA.

DCKO_TRM DCKOP/N Internal Termination On. When DCKO_TRM = 0, there is no internal termination at DCKOP/N.

When DCKO_TRM = 1, there is 100 between DCKOP and DCKON.

Note: Register 0x02 resets to 0x00 (default).

voltage swing of the DAC. For example, loading both IOUTP

and IOUTN with external 50 resistors to GND will cause

RLOAD to equal 25. Assuming an IOUTFS of 40mA, VDIFF

will swing between 1V and –1V.

The specified output compliance voltage range is ±1V.

Above 1V, the differential current steering switches will

start to approach the transition from saturation to linear

region and degrade DAC linearity. Below –1V protection

diodes will limit the swing of the DAC. Small voltage

swings and low common-mode voltages typically result

in the best distortion performance.

DAC Sample Clock (CKP/N)

The DAC sample clock (CKP/N) is used to update the

LTC2000A outputs at rates of up to 2.7Gsps. Provide a

clean, low jitter differential clock at up to 2.7GHz on pins

CKP/N (see Generating the DAC Sample Clock section).

The DC bias point of CKP/N is set internally through a

5k impedance. A 0dBm DAC sample clock should be

sufficient to obtain the performance shown in the Typical

Performance Characteristics section. For best jitter and

phasenoise,ACcoupleadifferentialclockontoCKP/Nwith

balanced duty cycle and the highest possible amplitude

and slew rate.

Use SPI register 0x02 to control the DAC sample clock

receiver(Table3).TheLTC2000Acontainsaclockdetector

which sets CK_OK = 1 if the DAC sample clock is present

and fDAC > 50MHz. When the sample clock is not present

(CK_OK = 0), the DAC output is forced to mid-scale and

the internal data path is held at reset. Set CK_PD = 1 to

power down the clock receiver and save power when the

DAC is not being used. Note that at power-on reset, the

DAC sample clock receiver is on by default.

Divided Clock Output (DCKOP/N)

The LTC2000A contains a programmable clock divider

and LVDS transmitter which provide a divided version

(either fDAC/4 or fDAC/2) of the DAC sample clock for

use by the host FPGA or ASIC. Use SPI register 0x02 to

control DCKOP/N (Table 3). At power-on reset, the LVDS

transmitter will provide a clock signal at fDAC/4 with a

3.5mA differential output current.

If desired, set DCKO_DIV = 1 to change the divided clock

output frequency to fDAC/2. The output current can be in-

creased to 7mA by setting DCKO_ISEL = 1, and an internal

100 differential termination can be enabled by setting

DCKO_TRM = 1. Set DCKO_DIS = 1 to disable the LVDS

transmitter and save power when not in use.

LVDS Data Clock Input (DCKIP/N)

The DAC code data written to the LTC2000A is captured

on both the rising and falling edges of DCKIP/N. For

single-port operation, provide a DDR clock at half the DAC

sample clock frequency (fDCKI = fDAC/2). To use a 1.35GHz

sample clock in single-port mode, provide a 675MHz

clock on DCKIP/N. For dual-port operation, provide a

DDR clock at one quarter the DAC sample clock frequency

(fDCKI = fDAC/4). To use a 2.7GHz sample clock in dual-port

mode, provide a 675MHz clock on DCKIP/N.

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