LTC6946 datasheet(27/54 Pages) LINER

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LTC2000A

2000afb

For more information www.linear.com/LTC2000A

OPERATION

Table 4. LVDS Clock SPI Registers

ADDRESS

BIT

NAME

DESCRIPTION

0x03

DCKI_EN

DCKIP/N Clock Receiver Enable. DCKI_EN = 1 enables LVDS clock receiver.

DCKI_OK

DCKIP/N Clock Present Indicator. When DCKI_OK = 1, clock is present at DCKIP/N pins and fDCKIP/N > 25MHz.

When DCKI_OK = 0, DAC output is forced to mid-scale unless pattern generator is enabled (PGEN_EN = 1).

DCKI_OK is read only.

DCKI_Q

DCKIP/N Quadrature Phase Select. For DCKI_Q = 0, DCKIP/N should be in phase with DAP/N and DBP/N.

Set DCKI_Q = 1 to use DCKIP/N in quadrature with DAP/N and DBP/N.

[6:4] DCKI_TADJ DCKIP/N Delay Adjust. Use with DCKI_Q = 0 to adjust delay of DCKIP/N relative to DAP/N and DBP/N.

For DCKI_Q = 1, DCKIP/N delay matches DAP/N and DBP/N and is unaffected by DCKI_TADJ.

DCKI_TADJ

NOMINAL DCKIP/N DELAY

DCKI_Q = 1

DCKI_Q = 0

110

0ps

230ps

111

0ps

315ps

000

0ps

400ps (Default)

001

0ps

485ps

010

0ps

570ps

Note: Register 0x03 resets to 0x00 (default).

Use SPI register 0x03 to control the LVDS data clock input

(see Table 4). Setting DCKI_EN=1 will enable the LVDS re-

ceiveratDCKIP/N.TheLTC2000Acontainsaclockdetector

which sets DCKI_OK=1 if the data input clock is present

and has a frequency greater than 25MHz (fDCKI > 25MHz).

When the data clock is not present (DCKI_OK = 0), the

DAC output is forced to mid-scale and the internal data

path is held at reset.

For maximum setup/hold margin, set DCKI_Q = 1 and

provide DCKIP/N in quadrature (90° out of phase) with

the data on DAP/N and DBP/N (Figure 3 in the Timing

Diagrams section). For DCKI_Q = 1, the internal delays

on DCKIP/N, DAP/N, and DBP/N are nominally matched.

Alternatively, it is possible to leave DCKI_Q= 0 and provide

the clock at DCKIP/N in phase with the data on DAP/N

and DBP/N (see Figure 2 of the Timing Diagram section).

In this case, an internal 400ps delay on DCKIP/N is used

to provide setup/hold margin. Note that for DCKI_Q = 0,

supply and temperature variation may reduce the setup/

hold margin on the bus by up to 150ps. If desired, users

may use the DCKI_TADJ bits in register 0x03 to adjust

the 400ps internal DCKIP/N delay with a typical resolu-

tion of 85ps.

Board trace lengths on DCKIP/N, DAP/N, and DBP/N must

be carefully matched to ensure that phase alignment is

maintained on all inputs. If desired during development,

usersmayobservetherelativetimingofneighboringLVDS

inputs on the TSTP/N pins (refer to the Measuring LVDS

Input Timing Skew section).

LVDS Data Input Ports (DAP/N, DBP/N)

The LTC2000A-16/LTC2000A-14/LTC2000A-11 allow for

DAC Code Data to be applied through one or two parallel

16-/14-/11-bit LVDS ports (DAP/N, DBP/N). Each port can

run up to 1.35Gbps using a double-data-rate (DDR) LVDS

data clock (DCKIP/N) at frequencies up to 675MHz. The

data input format is two’s complement.

There are two modes of operation for applying the DAC

code to the LTC2000A — single-port mode and dual-

port mode. Single port operation uses only LVDS port B

(DBP/N) and allows sample rates of up to 1.35Gsps. Dual

port operation uses both LVDS ports (DAP/N and DBP/N)

and allows sample rates up to 2.7Gsps.

Use SPI register 0x04 to control the LVDS data input

ports (see Table 5). After the clocks have stabilized and

the synchronizer has initialized itself, set DATA_EN = 1

to allow the data from ports A and B to be used to update

the DAC code. Clear DATA_EN = 0 to mute the DAC and

force the DAC code to mid-scale as desired.

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