LTC6946 datasheet(20/54 Pages) LINER

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LTC2000A

2000afb

For more information www.linear.com/LTC2000A

OPERATION

Note that the sample clock (CKP/N) frequency is always

four times the DDR data input clock (DCKIP/N) frequency

indual-portmode.Forexample,tousetheDACat2.7Gsps,

apply a 2.7GHz clock to CKP/N and a 675MHz clock to

DCKIP/N and send data into both ports A and B (DAP/N,

DBP/N) at 1.35Gsps per port.

LatencyisdefinedasthedelayfromtheDCKIP/Ntransition

that samples a DAC code to the CKP/N rising transition

which causes that sample to appear at the DAC output

IOUTP/N. In dual-port mode the latency from DAP/N to

IOUTP/N is 10 sample clock cycles and the latency from

DBP/N to IOUTP/N is 11 cycles, starting from the CKP/N

rising edge that immediately follows the DCKIP/N transi-

tion that sampled the DAC code (Figure 4b).

Single-Port Mode

In single-port mode, data is written to port B (DBP/N) only,

allowing DAC output sampling rates of up to 1.35Gsps.

Figures 4c and 4d show a block diagram and sample

waveformsrepresentingsingle-portoperation.Samplesare

written to port B (DBP/N) and sampled on both the falling

and rising edges of the DDR data input clock (DCKIP/N) by

two groups of flip-flops. The contents of these flip-flops

are then interleaved into a single data stream by the 2:1

MUX and sampled by the DAC sample clock (CKP/N) at

frequencies up to 1.35GHz.

Notethatinsingle-portmodethesampleclock(CKP/N)fre-

quencyisalwaystwicetheDDRdatainputclock(DCKIP/N)

frequency. For example, to use the DAC at 1.35Gsps, apply

a 1.35GHz clock to CKP/N and a 675MHz clock to DCKIP/N

and send data into port B (DBP/N) at 1.35Gsps. In single-

port mode, port A (DAP/N) should be grounded. Due to

the design of the internal clock synchronizer in single port

mode, there is a half cycle shift in the single port latency.

The latency from DBP/N to IOUTP/N in single-port mode is

7.5 sample clock cycles, starting from the CKP/N falling

edge that immediately follows the DCKIP/N transition that

sampled the DAC code (Figure 4d).

After incoming data is sampled by DCKIP/N, an internal

multiplexer interleaves the data for resampling by the

DAC sample clock (CKP/N). See Figures 4a and 4b. After

a pipeline delay (latency) of up to 11 DAC sample clock

cycles, the rising edges of CKP/N update the DAC code

and a proportional differential output current is steered

between the two outputs (IOUTP/N). Note it takes about 3ns

(aperture delay) from the CKP/N rising edge that updates a

DACcodetotheactualIOUTP/NtransitionforthatDACcode.

An internal clock synchronizer monitors the incoming

phase of DCKIP/N and chooses the appropriate phase for

the multiplexer control signals to ensure that the data is

sampledcorrectlybyCKP/N.TheLTC2000Aalsogenerates

an LVDS clock output (DCKOP/N) by dividing the sample

clock frequency to simplify clocking of the host FPGA

or ASIC. Additional features such as pattern generation,

LVDS loopout, and junction temperature sensing simplify

system development and testing.

The serial peripheral interface (SPI) port allows configura-

tion and read back of the internal registers which control

the above functions.

Dual-Port Mode

In dual-port mode, data is written to both ports A and B

simultaneously and then subsequently interleaved inside

the LTC2000A, allowing DAC output sampling rates of up

to 2.7Gsps. Figures 4a and 4b show a simplified block

diagram and sample waveforms for dual-port operation.

The LVDS data input ports A and B are sampled on both

the falling and rising edges of the DDR data input clock

(DCKIP/N) by four groups of flip-flops. The contents of

these flip-flops are then interleaved by the 4:1 MUX and

sampled by the DAC sample clock (CKP/N) at frequencies

up to 2.7GHz, with data from port A (DAP/N) preceding

data from port B (DBP/N) at the DAC output.

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