LTC6946 datasheet(30/54 Pages) LINER

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LTC2000A

2000afb

For more information www.linear.com/LTC2000A

OPERATION

Minimizing Harmonic Distortion

The LTC2000A contains proprietary dynamic linearization

circuitry which dramatically reduces 3rd order harmonic

distortion in the DAC output. SPI registers 0x07 and 0x08

are used to control these circuits (see Table 7). Optimal

performanceisnormallyachievedbysettingLIN_VMXand

LIN_VMN (register 0x08) to correspond to the maximum

and minimum voltages expected at IOUTP/N. At power-on

reset the default values are 0b1000 and 0b0000, which

are appropriate for IOUTP/N swinging between 500mV and

GND. If an application requires a different voltage swing,

LIN_VMX and LIN_VMN can be programmed by writing

to register 0x08 (see Table 7). For applications in which

IOUTP/N swing below GND, use LIN_VMN = 0b0000.

Insomeapplicationswhere2-toneintermodulationdistor-

tion (IMD) is a critical specification, it may be desired to

varytheamountof3rdorderharmoniccorrection.Forhigh

sampling frequencies (fDAC > 2Gsps), adjusting LIN_GN

in register 0x07 (see Table 7) can improve 2-tone inter-

modulation distortion at the expense of higher 3rd order

harmonic distortion. For best IMD performance at high

sampling frequencies, users may also choose to disable

dynamic linearization by setting LIN_DIS = 1. SFDR and

IMD curves in the Typical Performance Characteristics

section show more detail regarding this effect. Note that

for fDAC < 2Gsps, it is recommended to leave the dynamic

linearization enabled.

Measuring LVDS Input Timing Skew

It is important to ensure that the LVDS inputs (DCKIP/N,

DAP/N, DBP/N) are well aligned. Skew between clock and

data lines, for example due to board trace length mismatch

or output timing mismatch inside the host FPGA or ASIC,

will degrade the setup and hold margin of the incoming

data. The LTC2000A includes an internal test multiplexer

which may be used during development to verify timing

alignment by comparing the timing of LVDS inputs one

pair at a time through the TSTP/N pins.

Use SPI register 0x18 to control this test multiplexer (see

Table 8). Be sure TDIO_EN = 0 in register 0x19 and then

set LMX_EN = 1 to enable the test multiplexer output.

The signal from the LVDS data input will be driven onto

TSTP/N by an NMOS differential pair steering a 6.6mA

sink current onto an external load. Connect a pair of 50

resistors from TSTP/N to 3.3V and observe TSTP/N on a

high speed oscilloscope.

Apply clocks to CKP/N and DCKIP/N and apply the pattern

shown in Figure 8 to port B for single-port mode or ports

A and B for dual-port mode. This pattern is designed to

simplify comparison of rising-to-rising and falling-to-

falling edge timing for each input pair. Set LMX_ADR to

select a pair of LVDS inputs for timing comparison. Set

LMX_MSEL = 0 to observe the first signal at TSTP/N. Set

LMX_MSEL = 1 to observe the second signal with inverted

output polarity.

For example, to compare DB15P/N to DCKIP/N, first write

0x60 to register 0x18 to set LMX_EN = 1, LMX_ADR =

10000, and LMX_SEL = 0. The signal from DB15P/N will

be driven onto TSTP/N. Write 0x61 to register 0x18 to set

LMX_SEL = 1 and cause DCKIP/N to appear at TSTP/N

with inverted polarity.

Record the skew between the two signals and repeat

this measurement for each pair of inputs. After all pairs

have been measured, add the skews to calculate the total

skew from DCKIP/N to each data input (DAP/N, DBP/N).

In this way the skew of all LVDS data inputs (DAP/N,

DBP/N) relative to DCKIP/N can be accurately measured

to within 100ps.

Note that due to internal delays inside the test multiplexer,

it is only valid to compare timing between neighboring

LVDS pairs using the same LMX_ADR setting. Similarly,

themultiplexeritselfcontainsupto400psofskewbetween

rising and falling edges, so it is only valid to compare the

timing of a rising edge at TSTP/N to another rising edge,

and a falling edge to another falling edge.

Note that Figure 8 shows the suggested input pattern

for the LTC2000A-16. LTC2000A-14 users should apply

codes 0x1555 and 0x2AAA, and LTC2000A-11 users

should apply codes 0x555 and 0x2AA. Also note that for

the LTC2000A-14 and LTC2000A-11 in dual-port mode,

the timing skew of LVDS port A (DAP/N) cannot be com-

pared to that of the LVDS clock (DCKIP/N) and LVDS port

B (DBP/N), as there is no single test multiplexer address

(LMX_ADR) that enables a timing comparison between

signals DA0N/P and DCKIP/N (see Table 8). It is recom-

mended to keep LMX_EN=0 during normal operation.

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